• Title/Summary/Keyword: power dissipation

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Initial Characteristics of Generator Stator Insulations (발전기 고정자 권선 절연재료의 초기특성)

  • Lee, Young-Jun;Kim, Hee-Dong
    • Proceedings of the KIEE Conference
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    • 1999.07e
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    • pp.2110-2113
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    • 1999
  • This paper describes the initial characteristics of turbine generators at the Taean thermal power plant #4 and Wolsong nuclear power plant #2. The turbine generators had been in service for two years. The insulation diagnostic tests included measurements of insulation resistance, polarization index, ac current, dissipation factor($tan{\delta}$) and partial discharges (PD). The values of ac current and tan a were measured by Schering bridge. PD measurements were conducted using digital PD detector. The variation of $tan{\delta}$ and PD was confirmed in two generator stator insulations.

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Design of an 8 bit CMOS low power and high-speed current-mode folding and interpolation A/D converter (8비트 저전력 고속 전류구동 폴딩.인터폴레이션 CMOS A/D 변환기 설계)

  • 김경민;윤황섭
    • Journal of the Korean Institute of Telematics and Electronics C
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    • v.34C no.6
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    • pp.58-70
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    • 1997
  • In this paper, an 8bit CMOS low power, high-speed current-mode folding and interpolation A/D converter is designed with te LG semicon $0.8\mu\textrm{m}$ N-well single-poly/double-metal CMOS process to be integrated into a portable image signal processing system such as a digital camcoder. For good linearity and low power consumption, folding amplifiers and for high speed performance of the A/D converter, analog circuitries including folding block, current-mode interpolation circuit and current comparator are designed as a differential-mode. The fabricated 8 bit A/D converter occupies the active chip area of TEX>$2.2mm \times 1.6mm$ and shows DNL of $\pm0.2LSB$, INL of <$\pm0.5LSB$, conversion rate of 40M samples/s, and the measured maximum power dissipation of 33.6mW at single +5V supply voltage.

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The Study on Design of the CMOS Cascode LNA (CMOS 공정을 이용한 Cascode 구조의 LNA 설계)

  • Oh, Jae-Wook;Ha, Sang-Hoon;Kim, Hyeong-Seok
    • Proceedings of the KIEE Conference
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    • 2006.07c
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    • pp.1601-1602
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    • 2006
  • A cascode low noise amplifier(LNA) for a 2.45GHz RFID reader is designed using 0.25um CMOS technology. There are four LNA design techniques applied to the cascode topology. In this paper, power-constrained simultaneous noise and input matching(PCSNIM) technique is used for low power consumption and achieving the noise matching and input matching simultaneously. Simulation results demonstrate a noise figure of 2.75dB, a power gain of 10.17dB, and a dissipation power of 8.65mW with 1V supply.

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Zero Voltage Switching Boost H-Bridge AC Power Converter for Induction Heating Cooker

  • Kwon, Soon-Kurl;Saha, Bishwajit
    • Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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    • v.21 no.4
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    • pp.19-27
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    • 2007
  • This paper presents a novel soft-switching PWM utility frequency AC to high frequency AC power conversion circuit incorporating boost H-bridge inverter topology, which is more suitable and acceptable for cost effective consumer induction heating applications. The operating principle and the operation modes are presented using the switch mode equivalent circuits and the operating voltage and current waveforms. The performances of this high-frequency inverter using the latest IGBTs are illustrated, which includes high frequency power regulation and actual efficiency characteristics based on zero voltage soft-switching(ZVS) operation ranges, and the power dissipation as compared with those of the conventional type high frequency inverter. In addition, a dual mode control scheme of this high frequency inverter based on asymmetrical pulse width modulation(PWM) and pulse density modulation(PDM) control scheme is discussed in this paper in order to extend the soft switching operation ranges and to improve the power conversion efficiency at the low power settings. The power converter practical effectiveness is substantially proved based on experimental results from practical design example.

Electrical Characteristics of Insulation Paper for Distribution Transformers (배전변압기용 절연지의 전기적 특성)

  • Jung, J.W.;Song, I.K.;Lee, B.S.;Han, J.H.;Kweon, D.J.;Kim, C.Y.
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2001.05c
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    • pp.1-5
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    • 2001
  • This paper describes the electrical characteristics of Nomex paper employed as an insulating material of distribution transformers. The relative permittivities(dielectric constants) and $tan{\delta}$(dielectric dissipation factors) were measured as a dielectric characteristic and the partial discharge inception voltages(PDIVs) and breakdown voltages were also measured as an electrical strength characteristic of Nomex paper. As a result, the permittivity and $tan{\delta}$ of Nomex paper showed temperature and frequency dependency. Especially, the permittivity of 0.18mm Nomex paper was 2.4 according to the ASTM condition. And the PDIVs and breakdown voltages were, almost linearly increased with the thickness of Nomex paper and its electrical strength was better than conventional kraft paper.

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LOS/LOC Scan Test Techniques for Detection of Delay Faults (지연고장 검출을 위한 LOS/LOC 스캔 테스트 기술)

  • Hur, Yongmin;Choe, Youngcheol
    • The Journal of the Institute of Internet, Broadcasting and Communication
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    • v.14 no.4
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    • pp.219-225
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    • 2014
  • The New efficient Mux-based scan latch cell design and scan test of LOS/LOC modes are proposed for detection of delay faults in digital logic circuits. The proposed scan cell design can support LOS(Launch-off-Shift) and LOC(Launch-off-Capture) tests with high fault coverage and low scan power and it can alleviate the problem of the slow selector enable signal and hold signal by supporting the logic capable of switching at the operational clock speeds. Also, it efficiently controls the power dissipation of the scan cell design during scan testing. Functional operation and timing simulation waveform for proposed scan hold cell design shows improvement in at-speed test timing in both test modes.

Power Semiconductor SMD Package Embedded in Multilayered Ceramic for Low Switching Loss

  • Jung, Dong Yun;Jang, Hyun Gyu;Kim, Minki;Jun, Chi-Hoon;Park, Junbo;Lee, Hyun-Soo;Park, Jong Moon;Ko, Sang Choon
    • ETRI Journal
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    • v.39 no.6
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    • pp.866-873
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    • 2017
  • We propose a multilayered-substrate-based power semiconductor discrete device package for a low switching loss and high heat dissipation. To verify the proposed package, cost-effective, low-temperature co-fired ceramic, multilayered substrates are used. A bare die is attached to an embedded cavity of the multilayered substrate. Because the height of the pad on the top plane of the die and the signal line on the substrate are the same, the length of the bond wires can be shortened. A large number of thermal vias with a high thermal conductivity are embedded in the multilayered substrate to increase the heat dissipation rate of the package. The packaged silicon carbide Schottky barrier diode satisfies the reliability testing of a high-temperature storage life and temperature humidity bias. At $175^{\circ}C$, the forward current is 7 A at a forward voltage of 1.13 V, and the reverse leakage current is below 100 lA up to a reverse voltage of 980 V. The measured maximum reverse current ($I_{RM}$), reverse recovery time ($T_{rr}$), and reverse recovery charge ($Q_{rr}$) are 2.4 A, 16.6 ns, and 19.92 nC, respectively, at a reverse voltage of 300 V and di/dt equal to $300A/{\mu}s$.

A new continuous-time current-mode integrator for realization of low-voltage current-mode CMOS filter (저전압 전류모드 CMOS 필터 구현을 위한 새로운 연속시간 전류모드 적분기)

  • 방준호;조성익;김동용
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.21 no.4
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    • pp.1068-1076
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    • 1996
  • In this paper, a new continuous-time current-mode integrator as basic building block of the low-voltage analyog current-mode active filters is proposed. Compared to the current-mode integrator which is proposed by Zele, the proposed current-mode integrator had higher unity gain frequency and output impedance in addition to lower power dissipation. And also, a current-mode third-order lowpass active filter is designed with the proposed current-mode integrator. The designed circuits are fabricated using the ORBIT's $1.2{\mu}{\textrm{m}}$ deouble-poly double-metal CMOS n-well process. The experimental results show that the filter has -3dB cutoff frequency at 44.5MHz and 3mW power dissipation with single 3.3V power supply and also $0.12mm^{2}$ chip area.

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A Real Time Model of Dynamic Thermal Response for 120kW IGBT Inverter (120kW급 IGBT 인버터의 열 응답 특성 실시간 모델)

  • Im, Seokyeon;Cha, Gangil;Yu, Sangseok
    • Transactions of the Korean hydrogen and new energy society
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    • v.26 no.2
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    • pp.184-191
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    • 2015
  • As the power electronics system increases the frequency, the power loss and thermal management are paid more attention. This research presents a real time model of dissipation power with junction temperature response for 120kw IGBT inverter which is applied to the thermal management of high power IGBT inverter. Since the computational time is critical for real time simulation, look-up tables of IGBT module characteristic curve are implemented. The power loss from IGBT provides a clue to calculate the temperature of each module of IGBT. In this study, temperature of each layer in IGBT is predicted by lumped capacitance analysis of layers with convective heat transfer. The power loss and temperature of layers in IGBT is then communicated due to mutual dependence. In the dynamic model, PWM pulses are employed to calculation real time IGBT and diode power loss. Under Matlab/Simulink$^{(R)}$ environment, the dynamic model is validated with experiment. Results showed that the dynamic response of power loss is closely coupled with effective thermal management. The convective heat transfer is enough to achieve proper thermal management under guideline temperature.

Design and Implementation of Low-Power DCT Architecture by Minimizing Switching Activity (스위칭 엑티비티를 최소화한 저전력 DCT 아키텍쳐 구현)

  • Kim San;Park Jong-Su;Lee Yong-Joo;Lee Yong-Surk
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.31 no.6C
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    • pp.603-613
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    • 2006
  • Low-power design is one of the most important challenges encountered in maximizing battery life in portable devices as well as saving energy during system operation. In this paper we propose a low-power DCT (Discrete Cosine Transform) architecture using a modified Computation Sharing Multiplication (CSHM). The overall rate of Power consumption is reduced during DCT: the proposed architecture does not perform arithmetic operations on unnecessary bits during the Computation Sharing Multiplication calculations. Experimental results show that it is possible to reduce power dissipation up to about $7\sim8%$ without compromising the final DCT results. The proposed low-power DCT architecture can be applied to consumer electronics as well as portable multimedia systems requiring high throughput and low-power.