• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.5
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• pp.605-614
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• 2016

We develop a novel SAD circuit for power-efficient H.264 encoding, namely a-SAD. Here, some highest-order MSB's are approximated to single MSB. Our theoretical estimations show that our proposed design simultaneously improves performance and power of SAD circuit, achieving good power efficiency. We decide that the optimal number of approximated MSB's is four under 8-bit YUV-420 format, the largest number not to affect video quality and compression-rate in our video experiments. In logic simulations, our a-SAD circuit shows at least 9.3% smaller critical-path delay compared to existing SAD circuits. We compare power dissipation under iso-throughput scenario, where our a-SAD circuit obtains at least 11.6% power saving compared to other designs. We perform same simulations under two- and three-stage pipelined architecture. Here, our a-SAD circuit delivers significant performance (by 13%) and power (by 17% and 15.8% for two and three stages respectively) improvements.

• Proceedings of the KSR Conference
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• 1999.05a
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• pp.328-335
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• 1999

Three phase full bridge rectifier has been used to obtain dc voltage from three phase ac voltage source. The rectifier system has drawbacks that power factor is low and power flow is unidirectional. Therefore, when dc voltage increases due to regeneration of power the dynamic resister for dissipation of regeneration power must be installed. But three phase PWM converter can be controlled to operate with unity power factor and bidirectional power flow. Therefore when the PWM converter is used as do supply system, the dissipating resistor is not necessary. On this thesis, in order to design a controller having good performance, the hee phase PWM converter is completely modeled by using circuit DQ-transformation and thus a general and simple instructive equivalent circuit is obtained; the inductor set becomes a second order gyrator-coupled system and three phase inverter becomes a transformer as well. Under given phase angle(${\alpha}$) and modulation index(MI) of the three phase inverter, the dc and ac characteristics are obtained by analysis of the transformed equivalent circuit The validity of the equivalent circuit is confirmed through PSPICE simulation. And based on the dc and ac characteristics a controller with unity power factor is proposed.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.8
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• pp.42-45
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• 2002

A low power SDRAM output buffer with reduced power line noise and feedthrough current is presented. In multi I/O SDRAM output buffer, feedthrough current as well as the corresponding power dissipation are reduced utilizing proposed undershoot protection circuits. Ground bounce is minimized by the pull down driver using intelligent feedback scheme. Ground bounce noise is reduced by 66.3% and instantaneous and average power are reduced by 27.5% and 11.4%, respectively.

• Journal of Power Electronics
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• v.10 no.4
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• pp.374-381
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• 2010

Typical power electronic converters employ only pulse width modulation (PWM) to generate specific switching patterns. In this paper, a novel control strategy combining both pulse-width and amplitude modulation strategies (PWAM) has been proposed for power converters. The Pulse Amplitude Modulation (PAM), used in communication systems, has been applied to power electronic converters. This increases the degrees of freedom in eliminating or mitigating harmonics when compared to the conventional PWM strategies. The role of PAM in the novel PWAM strategy is based on the control of the converter's dc sources values. Software implementation of the conventional PWM and the PWAM control strategies has been applied to a five-level inverter for mitigating selective harmonics. Results show the superiority of the proposed strategy from the THD point of view along with a reduction in the inverter power dissipation.

• The Transactions of the Korean Institute of Power Electronics
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• v.28 no.1
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• pp.39-47
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• 2023

This paper applies a structural technique with uniform parallel switch characteristics in gates and power loops to minimize the ringing and current imbalance that occurs when a general discrete package (TO-247)-based power semiconductor device is operated in parallel. Also, this propose a heat sink integrated switching module with heat sink design flexibility and high power density. The developed heat dissipation-integrated switching module verifies the symmetry of the parasitic inductance of the parallel switch through Q3D by ansys and the validity of the structural technique of the parallel switch using the LLC resonant converter experiment operating at a rated capacity of 7.5 kW.

• Current Photovoltaic Research
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• v.6 no.2
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• pp.39-42
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• 2018

When the PV module is illuminated in a high temperature region, solar cells are also exposed to the high temperature external environment. The operating temperature of the solar cell inside the module is increased, which causes the power drops. Various efforts have been made to reduce the operating temperature and compensate the power of solar cells according to the outdoor temperature such as installing of a cooling system. Researches have been also reported to lower the operating temperature of solar cells by improving the heat dissipation properties of the backsheet. In this study, we conducted a test to measure the internal temperature of each module components and the external temperature when the light was irradiated according to the surrounding temperature. Backsheets with different thermal conductivities were compared in the test. Finally, in order to explain the temperature difference between the solar cell and the outside of the module, we proposed an evaluation method of the heat transfer characteristics of photovoltaic modules with different backsheet.

• Transactions of Materials Processing
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• v.10 no.4
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• pp.347-354
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• 2001

Compression tests were carried out to investigate the hot-deformation behavior of Ti-6Al-4V alloy in the temperature range of $915^{\circ}C$ to $1015^{\circ}C$ and the strain rate range of $10^{-3}s^{-i}$ to $10s^{-1}$. Under the given test conditions, the hot-deformation of Ti-6Al-4V alloy was mainly led by dynamic recovery rather than by dynamic recrystallization. The activation energy for the plastic deformation in $\alpha+\beta$ field was about 894 kJ/mol and $\beta$ field was 332kJ/mo1. Processing map for hot working are developed on the basis of the variations of efficiency of power dissipation($\eta$=2m/m＋1) and flow instability criterion using the dynamic material model. The optimum process condition in the ($\alpha＋\beta$) field was obtained at the temperature ranges of $930^{\circ}C$ to $955^{\circ}C$$^{\circ}C$ and a strain rate of $10^{-3}s{-1}$.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.13 no.12
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• pp.1058-1062
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• 2000

We investigated resistive superconducting fault current limites (SFCLs) fabricated using YBCO thin films on 2-inch diameter sapphire substrates. Nearly identical SFCL units were prepared and tested. The units were connected in series and parallel to increase the current and voltage ratings. A serial connection of the units showed significantly unbalanced power dissipation between the units. This imbalance was removed by introducing a shunt resistor to the firstly quenched unit. Parallel connection of the units increased the current rating. An SFCL module of 4 units in parallel, each of which has minimum quench current rating. An SFCL module of 4 units in parallel, each of which has minimum quench current 25 A$\_$peak/, was produced and successfully tested at a 220 V$\_$rms/circuit. From the resistance increase, we estimated that the film temperature increased to 200 K in 5 msec, and 300 K in 120 msec. Successive quenches revealed that this system is stable without degradation in the current limiting capability under such thermal shocks as quenches at 220 V$\_$rms/.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2004.11a
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• pp.57-60
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• 2004

This paper presents multibit Sigma-Delta ADC using Leslie-Singh Structure to Improve nonlinearity of feedback loop. 4-bit flash ADC for multibit Quantization in Sigma Delta modulator offers the following advantages such as lower quantization noise, more accurate white-noise level and more stability over single quantization. For the feedback paths consisting of DAC, the DAC element should have a high matching requirement in order to maintain the linearity performance which can be obtained by the modulator with a multibit quantizer. Thus a Sigma-Delta ADC usually adds the dynamic element matching digital circuit within feedback loop. It occurs complexity of Sigma-Delta Circuit and increase of power dissipation. In this paper using the Leslie-Singh Structure for improving nonliearity of ADC. This structure operate at low oversampling ratio but is difficult to achieve high resolution. So in this paper propose improving loop filter for single-bit feedback multi-bit quantization Sigma-Delta ADC. It obtained 94.3dB signal to noise ratio over 615kHz bandwidth, and 62mW power dissipation at a sampling frequency of 19.6MHz. This Sigma Delta ADC is fabricated in 0.25um CMOS technology with 2.5V supply voltage.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.856-859
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• 2002

This paper proposes a high-performance VLSl architecture using distributed arithmetic for higher-order FIR filters with complex coefficients. For the purpose of realizing high sampling rate with small latency in high-order filters, we apply distributed arithmetic[1］. Moreover, in order to decrease drastically the power dissipation, the structure applying not ROM's but optimum function circuits which we have previously proposed, is utilized［2]［3］. However, this structure increases in the number of adders as compared to the conventional structure applying ROM's. In order to realize a more effective method for further higher-order filter, we propose newly an implementation applying two methods which have large effects on the unit using the adders. First , we propose an implementation applying SFAs(Serial Full Adders) and SFSs(Serial Full Subtractors). Second, we propose a structure applying proposed 4-2 adders. Finally, it is shown that the proposed architecture is an effective way to realize low power dissipation and small latency while the sampling rate is kept constant for further higher-order filters with complex coefficients.