• Journal of Electrical Engineering and Technology
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• 제6권5호
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• pp.671-676
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• 2011

A multilayer square-type piezoelectric transformer with a hole at the center was investigated in this paper. Temperature distribution at the center was improved by using this construction, therefore increasing input voltage and output power. This model was simulated and investigated successfully by applying a finite element method (FEM) in ATILA software. An optimized structure was then fabricated, examined, and compared to the simulation results. Electrical characteristics, including output voltage and output power, were measured at different load resistances. The temperature distribution was also monitored using an infrared camera. The piezoelectric transformer operated at first radial vibration mode and a frequency area of 70 kHz. The 16 W output power was achieved in a three-layer transformer with 96% efficiency and $20^{\circ}C$ temperature rise from room temperature under 115 V driving voltage, 100 ${\Omega}$ matching load, $28{\times}28{\times}1.8mm$ size, and 2 mm hole diameter. With these square-type multilayer piezoelectric transformers, the temperature was concentrated around the hole and lower than in piezoelectric transformers without a hole.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -1
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• pp.86-89
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• 2002

A new design approach for realising low-power low-voltage high-Q high-order RE bandpass filter is proposed. Based on the gyrator-C inductor topology, a 2$\^$nd/-order biquadratic bandpass filter can be realised by adding a series capacitor to the input port of the gyrator. High-Q 2$\^$nd/-order and 4$\^$th/-order fully differential RF bandpass filters operating in the 2.4-㎓ ISM (Industrial, scientific and medical) frequency band under a 2-V single power supply voltage with low power dissipation are reported.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2002년도 ITC-CSCC -2
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• pp.1280-1283
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• 2002

This paper discusses issues in VLSI design and implementation of high performance datapath circuits. Of particular concern will he various types of multiplier and adder, which are fundamental to DSP operations. Performance comparison will be provided in terms of sampling speed, layout area, and in particular, power consumption, with techniques that may be applied to reduce power dissipation also suggested. As an example, a low power, high performance recursive filter achieved through bit-level pipelining technique is illustrated

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2003년도 하계종합학술대회 논문집 II
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• pp.1019-1022
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• 2003

This paper has proposed a 4- bit 20MHz Flash A/D converter design available analog signal processing and realized its intergrated circuit. The parallel comparison method A/D converter quantized analog signals swiftly using various converters. Also this theme has designed economic power dissipation circuit using a preamplifier of low volt & power CMOS comparator. Also the system was fabricated by Hynix 0.35um CMOS process.

• 전자공학회논문지C
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• 제34C권11호
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• pp.12-19
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• 1997

In this paper, we present a logic synthesis algorithm for low powr design fo combinational circuits. The proposed algorithm reduces power dissipation by eliminating unnecessary signal transitions. The proposed algorithm restructures a given circuit by using a kernel as prediction logic in a precomputation-based scheme such that switching activity of circuit can be minimized. Experimental results show that the system is efficient for low power design of combinational circuits.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.149-152
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• 2001

In this paper, a 1.5V 2㎓ low-power peak detector is presented. Analyzing the designed peak detector circuit which is composed with two NMOSs, two diodes, and two capacitors, the detection characteristic relationships are derived. The simulation results with SPICE for 2㎓ pulse signals and sinusoidal signals on the 1.5V supply voltages show the good detection characteristics for input signal levels of 50㎷~500㎷, and show very small power dissipation of 0.332㎽.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 1999년도 추계종합학술대회 논문집
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• pp.967-970
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• 1999

A novel linear transconductor for low-voltage low-power signal processing is proposed. The transconductor consists of a pnp differential-pair and a npn differential-pair which are biased by local negative feedback. The simulation results show that the transcondcutor with transconductance of 50 $mutextrm{s}$ has a linearity error of 0.05% and the power dissipation is 2.44 ㎽ over an input linear range from -2V to +2V at supply voltage $\pm$3V.

• Journal of Magnetics
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• 제4권3호
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• pp.98-101
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• 1999

In this work we htave constructed an under water sonar transducer using Terfenol-D rod employing open magnetic circuit. Normally Sonar transducer using Terfenol-D was designed under closed magnetic flux return path, and permanent magnet for dc bias marnetic field, but high magnetic field should be applied to the transducer coil for high sound power and it brings temperature increase inside of the transducer. To improve this heat dissipation problem, we have designed an open magnetic circuit type transducer and we can get 200 dB (re. 1 Pa @ 1m) sound power for the input power of 650 VA.

• Geomechanics and Engineering
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• 제12권4호
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• pp.595-609
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• 2017

Due to high in-situ stress and brittleness of rock mass, the surrounding rock masses of underground caverns are prone to appear splitting failure. In this paper, a kind of loading-unloading variable elastic modulus model has been initially proposed and developed based on energy dissipation principle, and the stress state of elements has been determined by a splitting failure criterion. Then the underground caverns of Dagangshan hydropower station is analyzed using the above model. For comparing with the monitoring results, the entire process of rock splitting failure has been achieved through monitoring the splitting failure on side walls of large-scale caverns in Dagangshan via borehole TV, micro-meter and deformation resistivity instrument. It shows that the maximum depth of splitting area in the downstream sidewall of the main power house is approximately 14 m, which is close to the numerical results, about 12.5 m based on the energy dissipation model. As monitoring result, the calculation indicates that the key point displacement of caverns decreases firstly with the distance from main powerhouse downstream side wall rising, and then increases, because this area gets close to the side wall of main transformer house and another smaller splitting zone formed here. Therefore it is concluded that the energy dissipation model can preferably present deformation and fracture zones in engineering, and be very useful for similar projects.

• 한국전자통신학회논문지
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• 제18권4호
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• pp.641-648
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• 2023

최근 4차 산업 혁명 중에서 인공지능의 급성장은 반도체의 성능 향상 및 회로의 집적을 기반으로 진보하였다. 전자기기 및 장비의 내부에서 연산을 돕는 트랜지스터는 고도화 및 소형화 되어 가며 발열의 제어 및 방열의 효율 개선이 새로운 성능의 지표로 대두되었다. DUT(Device Under Test) Shell은 트랜지스터의 검수를 위하여 정격 전류를 인가한 후, 임의의 발열 지점에서 전원을 차단한 상태에서, 방열을 통하여 트랜지스터의 내구도를 평가하여 불량 트랜지스터를 검출하는 장비이다. DUT Shell은 장비 내부의 방열 구조에 따라 동시에 더 많은 트랜지스터를 테스트할 수 있기 때문에 방열 효율은 불량 트랜지스터 검출 효율과 직접적인 관계를 갖는다. 이에 본 논문에서는 DUT Shell의 방열 최적화를 위하여 배치구조의 다양한 방법을 제안하고 전산유체역학을 이용하여 최적의 DUT Shell의 다양한 변형과 열 해석을 제안하였다.