• Journal of the Institute of Electronics Engineers of Korea SD
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• v.42 no.2 s.332
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• pp.9-14
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• 2005

This paper reports the hot carrier induced RF performance degradation of bulk dynamic threshold voltage MOSFET (B-DTMOS) compared with bulk MOSFET (B-MOS). In the normal and moderate mode operations, the degradations of cut-off frequency $(f_{T})$ and minimum noise figure $(F_{min})$ of B-DTMOS are less significant than those of B-MOS devices. Our experimental results show that the RF performance degradation is more significant than the U performance degradation after hot carrier stressing. Also, the degradation characteristics of RF power Performance of B-DTMOS due to hot carrier effects are measured for the first time.

• Proceedings of the KIEE Conference
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• 2009.04b
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• pp.131-135
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• 2009

This paper reviews the characteristics of Power MOSFET device technology that are leading to improvements in power loss for power electronic system. The silicon bipolar power transistor has been displaced by silicon power MOSFET's in low and high voltage system. The power electronic technology requires the marriage of power device technology with MOS-gated device and bipolar analog circuits.

• The Transactions of the Korean Institute of Electrical Engineers P
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• v.67 no.3
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• pp.168-174
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• 2018

The performance test for 376MW ESS for frequency regulation currently operating in 13 substations is conducted based on the test procedure in the first and second steps. In the first step, components of ESS is moved to the certification authority where the test equipment is located in order to be proceeded with the test. In the second step, the performance test is conducted manually for the ESS equipments installed on site using the movable measurement equipment, and thus it can only be performed on some limited test items and requires a lot of time and manpower. Therefore, mobile test equipment for ESS(MOTES) is being developed that can perform automatically more test items for ESS in the field using the MOTES, and reduce manpower and time. To do this, an algorithm and a prototype of the operating system(MOS) are also being developed that can control MOTES automatically. In this paper, a development of the MOS prototype is introduced and then a simulation is performed to verify the prototype and its algorithm before the field demonstration.

• Journal of the Institute of Electronics and Information Engineers
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• v.53 no.5
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• pp.69-76
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• 2016

Current driving capability of MCT (MOS Controlled Thyristor) is determined by turn-off capability of conducting current, that is off-FET performance of MCT. On the other hand, having a good turn-on characteristics, including high peak anode current ($I_{peak}$) and rate of change of current (di/dt), is essential for pulsed power system which is one of major application field of MCTs. To satisfy above two requirements, careful control of on/off-FET performance is required. However, triple diffusion and several oxidation processes change surface doping profile and make it hard to control threshold voltage ($V_{th}$) of on/off-FET. In this paper, we have demonstrated the effect of $V_{th}$ adjustment ion implantation on the performance of MCT. The fabricated MCTs (active area = $0.465mm^2$) show forward voltage drop ($V_F$) of 1.25 V at $100A/cm^2$ and Ipeak of 290 A and di/dt of $5.8kA/{\mu}s$ at $V_A=800V$. While these characteristics are unaltered by $V_{th}$ adjustment ion implantation, the turn-off gate voltage is reduced from -3.5 V to -1.6 V for conducting current of $100A/cm^2$ when the $V_{th}$ adjustment ion implantation is carried out. This demonstrates that the current driving capability is enhanced without degradation of forward conduction and turn-on switching characteristics.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.34C no.4
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• pp.1-15
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• 1997

This paper proposes CMOS on-chip voltage and current reference circuits that operate at supply voltages between 2.5V and 5.5V without using a vonventional bandgap voltage structure. The proposed reference circuits based on enhancement-type MOS transistors show low cost, compatibility with other on-chip MOS circuits, low-power consumption, and small-chip size. The prototype was implemented in a 0.6 um n-well single-poly double-metal CMOS process and occupies an active die area of $710 um \times 190 um$. The proposed voltage reference realizes a mean value of 0.97 V with a standard deviation of $\pm0.39 mV$, and a temperature coefficient of $8.2 ppm/^{\circ}C$ over an extended temeprature range from TEX>$-25^{\circ}C$ to $75^{\circ}C$. A measured PSRR (power supply rejection ratio) is about -67 dB at 50kHz.

• Proceedings of the KIEE Conference
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• 1996.07c
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• pp.1579-1581
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• 1996

The high temperature characteristics of SOI BMFET are analyzed by the numerical simulation and compared with MOS-gated SOI power devices at high temperatures. The proposed SOI BMFET combines bipolar operation in the on-state with unipolar FET operation in the off-state, so that it may be suitable for high temperature operation without any significant degradation of performance such as the leakage current and blocking capability. The simulation results show that SOI BMFET with a higher doped n-resurf layer is the most promising device far high temperature application as compared with MOS-gated SOI power devices, exhibiting the low on-state voltage drop as well as the excellent forward blocking capability at high temperature.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.443-450
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• 2016

The linearization technique for low noise amplifier (LNA) has been implemented in standard $0.18-{\mu}m$ BiCMOS process. The MOS-BJT derivative superposition (MBDS) technique exploits a parallel LC tank in the emitter of bipolar transistor to reduce the second-order non-linear coefficient ($g_{m2}$) which limits the enhancement of linearity performance. Two feedback capacitances are used in parallel with the base-collector and gate-drain capacitances to adjust the phase of third-order non-linear coefficients of bipolar and MOS transistors to improve the linearity characteristics. The MBDS technique is also employed cascode configuration to further reduce the second-order nonlinear coefficient. The proposed LNA exhibits gain of 9.3 dB and noise figure (NF) of 2.3 dB at 2 GHz. The excellent IIP3 of 20 dBm and low-power power consumption of 5.14 mW at the power supply of 1 V are achieved. The input return loss ($S_{11}$) and output return loss ($S_{22}$) are kept below - 10 dB and -15 dB, respectively. The reverse isolation ($S_{12}$) is better than -50 dB.

• Proceedings of the IEEK Conference
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• 2002.07b
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• pp.1058-1061
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• 2002

This paper presents the method of low power optimization considering the glitch reduction in CMOS circuits. Our algorithm utilizes the information of MOS size, the load capacitance of fan-out, and input slew to calculate the output waveform by using the linear signal model. Therefore, the accurate waveform of glitch can be obtained for estimation of power dissipation caused by glitches. Our algorithm is applied to ISCAS’85 benchmark circuits and experimental results show 23% glitch reduction and 11% total power reduction.

• ETRI Journal
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• v.37 no.1
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• pp.97-106
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• 2015

In this paper, MOS-triggered silicon-controlled rectifier (SCR)-based electrostatic discharge (ESD) protection circuits for mobile application in 3.3 V I/O and SCR-based ESD protection circuits with floating N+/P+ diffusion regions for inverter and light-emitting diode driver applications in 20 V power clamps were designed. The breakdown voltage is induced by a grounded-gate NMOS (ggNMOS) in the MOS-triggered SCR-based ESD protection circuit for 3.3 V I/O. This lowers the breakdown voltage of the SCR by providing a trigger current to the P-well of the SCR. However, the operation resistance is increased compared to SCR, because additional diffusion regions increase the overall resistance of the protection circuit. To overcome this problem, the number of ggNMOS fingers was increased. The ESD protection circuit for the power clamp application at 20 V had a breakdown voltage of 23 V; the product of a high holding voltage by the N+/P+ floating diffusion region. The trigger voltage was improved by the partial insertion of a P-body to narrow the gap between the trigger and holding voltages. The ESD protection circuits for low- and high-voltage applications were designed using $0.18{\mu}m$ Bipolar-CMOS-DMOS technology, with $100{\mu}m$ width. Electrical characteristics and robustness are analyzed by a transmission line pulse measurement and an ESD pulse generator (ESS-6008).

• Journal of IKEEE
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• v.8 no.2 s.15
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• pp.172-180
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• 2004

In this paper, a parallel Input/Output modulo multiplier, which is applied to AOTP(All One or Two Polynomials) multiplicative algorithm over $GF(3^m)$, has been proposed using neuron-MOS Down-literal circuit on voltage mode. The three-valued input of the proposed multiplier is modulated by using neuron-MOS Down-literal circuit and the multiplication and Addition gates are implemented by the selecting of the three-valued input signals transformed by the module. The proposed circuits are simulated with the electrical parameter of a standard $0.35{\mu}m$CMOS N-well doubly-poly four-metal technology and a single +3V supply voltage. In the simulation result, the multiplier shows 4 uW power consumption and 3 MHzsampling rate and maintains output voltage level in ${\pm}0.1V$.