• 제목/요약/키워드: polysilicon

검색결과 324건 처리시간 0.022초

0.25 μm 표준 CMOS 로직 공정을 이용한 Single Polysilicon EEPROM 셀 및 고전압소자 (Single Polysilicon EEPROM Cell and High-voltage Devices using a 0.25 μ Standard CMOS)

  • 신윤수;나기열;김영식;김영석
    • 한국전기전자재료학회논문지
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    • 제19권11호
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    • pp.994-999
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    • 2006
  • For low-cost embedded EEPROM, in this paper, single polysilicon EEPROM and n-channel high-voltage LDMOST device are developed in a $0.25{\mu}m$ standard CMOS logic process. Using these devices developed, the EEPROM chip is fabricated. The fabricated EEPROM chip is composed of 1 Kbit single polysilicon EEPROM away and high voltage driver circuits. The program and erase characteristics of the fabricated EEPROM chip are evaluated using 'STA-EL421C'. The fabricated n-channel high-voltage LDMOST device operation voltage is over 10 V and threshold voltage window between program and erase states of the memory cell is about 2.0 V.

텅스텐 폴리사이드를 이용한 게이트 산화막의 절연특성 개선에 관한연구 (A study on the dielectric characteristics improvement of gate oxide using tungsten policide)

  • 엄금용;오환술
    • 전자공학회논문지D
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    • 제34D권6호
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    • pp.43-49
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    • 1997
  • Tungsten poycide has studied gate oxide reliability and dielectric strength charactristics as the composition of gate electrode which applied submicron on CMOS and MOS device for optimizing gate electrode resistivity. The gate oxide reliability has been tested using the TDDB(time dependent dielectric breakdwon) and SCTDDB (stepped current TDDB) and corelation between polysilicon and WSi$_{2}$ layer. iN the case of high intrinsic reliability and good breakdown chracteristics on polysilicon, confirmed that tungsten polycide layer is a better reliabilify properities than polysilicon layer. Also, hole trap is detected on the polysilicon structure meanwhile electron trap is detected on polycide structure. In the case of electron trap, the WSi$_{2}$ layer is larger interface trap genration than polysilicon on large POCL$_{3}$ doping time and high POCL$_{3}$ doping temperature condition. WSi$_{2}$ layer's leakage current is less than 1 order and dielectric strength is a larger than 2MV/cm.

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고로슬래그와 폴리실리콘 슬러지의 비율에 따른 무기결합재의 역학적 특성 (Dynamic Properties of the Inorganic Binder Based on Blast Furnace Slag and Polysilicon Sludge ratio)

  • 임정근;이지환;박희곤;이상수
    • 한국건축시공학회:학술대회논문집
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    • 한국건축시공학회 2014년도 추계 학술논문 발표대회
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    • pp.146-147
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    • 2014
  • The environmental pollution problem the globally related to global warming arises, the demand for the solar power generation increases. But is generated sludge about 2tons in order to produce 1ton in the solar power generation used main material polysilicon. In this way, the arising sludge there is not method recycling and it is all discarded. Therefore, in this research, cement is not used dynamic properties tries to be analyze inorganic binder based on blast furnace slag and polysilicon sludge ratio. The appropriate replacement ratio of the experimental result polysilicon sludge was to be 8%.

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P+ Polysilicon층 위에 저압화학증착된 $WSi_{x}$ 박막의 열처리에 따른 전기적 특성 (Electrical Properties of Annealed $WSi_{x}$ Films Deposited on P+ Polysilicon by LPCVD)

  • 이희승;임호빈;이종무
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1990년도 추계학술대회 논문집
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    • pp.81-85
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    • 1990
  • $WSi_{x}$ film deposited on p+ polysilicon by low pressure chemical vapor deposition method were annealed by rapid thermal process, their properties have been investigated by measurements of electrical resistivity and Hall voltage and by analyses of phases and microstructure using X-ray diffraction and SEM technique. The electrical resistivity of the polycides consisting of the tungsten silicide and the p+ polysilicon decreases with the increase in annealing temperature due probably to the increase in grain size. unlike the polycides consisting of the $WSi_{x}$ and n+ polysilicon, however, the Hall voltage of the polycides consisting of $WSi_{x}$ and p+ polysilicon were positive for all specimens annealed as well as the as-deposited one, indicating the majority carrier in $WSi_{x}$. is hole and is independent of the annealing.

다결정 실리콘 마이크로머시닝 제작 시 폴리머 지지를 이용한 옆 방향 정착방지 방법의 제안 (A New Antistiction Method Using Polymer Suspension for Fabrication with Polysilicon Micromachining)

  • 임형택;윤종현;김용권
    • 대한전기학회:학술대회논문집
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    • 대한전기학회 1999년도 하계학술대회 논문집 G
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    • pp.3331-3333
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    • 1999
  • A novel antistiction method using photo resist is proposed and verified to improve the yield of polysilicon micromachining process. $7.5{\mu}m-thick$ polysilicon is used as a structural layer. Residual stress and stress gradient originated from polysilicon deposition with LPCVD process is relaxed by doping and thermal treatment. The stress gradient of stress-free polysilicon layer is $-0.755MPa/{\mu}m$.

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A Study on Pumping Effect of Oxygen in Polysilicon Gate Etching

  • Kim, Nam-Hoon;Shin, Sung-Wook;Bin, Shin-Seok;Yu chang-Il kim;Chang, Eui-Goo
    • Transactions on Electrical and Electronic Materials
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    • 제1권2호
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    • pp.1-6
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    • 2000
  • This article presents the experiments and considerations possible about gate etching in polysilicon when oxygen gas is added in chamber, We propose the novel study with optical emission spectroscopy in polysilicon etching. It is shown that added oxygen gases play an important role in enhencement of density in chlorine gases as a scavenger of silicon from SiCl$\_$x/. And a small amount of Si-O bonds are deposited and then the deposited thin film protect silicon dioxyde against reaction chlorine with silicon in SiO$_2$. Consequently, we can improve the selectivity of polysilicon the silicon dioxide, which is clearly explained in this model.

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열풍동형 폴리실리콘 마이크로 액츄에이터의 제작 및 특성 분석 (Fabrication of thermally driven polysilicon micro actuator and its characterization)

  • 이종현
    • 한국정밀공학회:학술대회논문집
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    • 한국정밀공학회 1996년도 춘계학술대회 논문집
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    • pp.146-150
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    • 1996
  • A thermal micro actualtor has been fabricated using surface micromachining techniques. It consists of doped ploysilicon as a moving part and TEOS(Tetra Ethyl Ortho Silicate) as a sacrificial layer. The polysilicon was annealed for the reduction of residual stress which is the main cause to its deformation such as bending and buckling. And the newly developed HF VPE(vapor phase etching)process was also used as an effective release method for the elimination of sacrificaial layer. With noliquid involved during any of the steps for relasing, unlike other reported relase techniques, the HF VPE pocess has produced polysilicon microstructures with virtually no process-induced stiction problem. The actuation is incured by the thermal expasion due to current flow in active polysilicon cantilever, which motion is amplified bylever mechanism. The thickness of pllysilicon is 2 .mu. m and the length of active and passive polysilicon cantilever are 500 .mu. m, respectively. The moving distance of polysilicon actuator was experimentally conformed as large as 21 .mu. m at the input voltage level of 10 V and 50Hz square wave. These micro actuator technology can be utilized for the fabrication of MEMS (microlectromechanical system) such as microrelay, which requires large displacement or contact force but relatively slow response.

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공정조건에 따른 함몰된 다결정실리콘/실리콘($n^{+}$) - 실리콘(p) 접합의 특성 (Properties of Recessed Polysilicon/Silicon($n^{+}$) - Silicon(P) Junction with Process Condition)

  • 이종호;최우성;박춘배;이종덕
    • 한국전기전자재료학회:학술대회논문집
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    • 한국전기전자재료학회 1994년도 춘계학술대회 논문집
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    • pp.152-153
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    • 1994
  • A recessed $n^{+}$-p junction diode with the serf-aligned structure is proposed and fabricated by using the polysilicon as an $n^{+}$ diffusion source. The diode structure can be applicable to the emitter-base formation of high performance bipolar device and the $n^{+}$ polysilicon emitter has an important effect on the device characteristics. The considered parameters for the polysilicon formation are the deposition condition $As^{+}$ dose for the doping of the polysilicon, and the annealing using RTP system. The vertical depth profiles of the fabricated diode are obtained by SIMS. The eleotrical characteristics are analyzed in trims of the ideality factor of diode (n), contact resistance arid reverse leakage current. The $As_{+}$ dose for the formation of good junction is current. The $As^{+}$ dose for the formation of goodjunctions is about 1∼2${\times}$$10^{16}$$cm^{-2}$ at given RTA condition ($1100^{\circ}C$, 10 sec). The $n^{+}$-p structure is successfully applied to the self-aligned bipolar device adopting a single polysilicon technology.

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마이크로 공진 구조체 제작을 위한 다층 폴리실리콘의 스트레스 특성 (Stress characteristics of multilayer polysilicon for the fabrication of micro resonators)

  • 최창억;이창승;장원익;홍윤식;이종현;손병기
    • 센서학회지
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    • 제8권1호
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    • pp.53-62
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    • 1999
  • MEMS(Microelectromechanical System) 기술분야에서 폭넓게 사용하고 있는 폴리실리콘 박막을 이용하여 폴리실리콘 미소 공진 구조체를 제작하였다. 폴리실리콘 증착은 저압기상화학증착 장비를 사용하여 대칭적 두께로 박막을 적층하였고 폴리실리콘의 응력과 응력구배를 최소화시키기 위한 적층, 도핑 방법 및 열처리에 따른 특성을 분석하였다. 이를 위하여 브리지 빔과 캔티레바 테스트 패턴을 제작하여 기계적 응력 특성을 측정하였으며, 아울러 공정 조건별 개별 시료에 대한 물성을 XRD, SIMS등으로 분석하였다. 공진 구조체는 대칭적 증착 구조를 가지며, 최종적으로 $6.5{\mu}m$의 두께로 적층되었다. 제작된 평면형 공진 구조체의 진동특성은 직류 15V, 교류 0.05V의 구동전압, 1000mtorr 압력에서 공진 진폭이 $5{\mu}m$ Q값이 1270임을 보였으며, 개발된 마이크로 폴리실리콘 공진체는 마이크로 자이로 및 가속도 센서에 응용될 수 있다.

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금속 외팔보에 접착된 박막 실리콘 스트레인 게이지의 제작 및 성능 평가 (Fabrication and Performance Evaluation of Thin Polysilicon Strain Gauge Bonded to Metal Cantilever Beam)

  • 김용대;김영덕;이철섭;권세진
    • 대한기계학회논문집A
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    • 제34권4호
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    • pp.391-398
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    • 2010
  • 금속은 가공성이 우수하기 때문에 다양한 형태의 구조물이나 격막을 제작할 수 있다. 이런 금속 구조물이나 격막에 민감도가 월등히 우수한 실리콘 스트레인 게이지를 적용할 경우 그 응용 범위가 다양해질 수 있다. 이에 금속구조물에 다결정 실리콘 스트레인 게이지를 접착한 형태의 센서를 제안하였다. 실리콘 기판을 이용해 박막형 다결정 실리콘 스트레인 게이지를 제작하기 위한 제작공정을 확립하였으며, 제작된 실리콘 스트레인 게이지를 금속 변형부 위에 접착하기 위한 접착공정을 확립하였다. 이후 금속 외팔보에 실리콘 스트레인 게이지를 글래스 프릿 접착하여 성능평가를 실시하였다. 성능평가 결과 게이지팩터는 34.0 의 값을 가졌으며, TCR(Temperature Coefficient of Resistance)은 $-328\;ppm/^{\circ}C$의 값을 가졌다.