• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2010년도 하계학술대회 논문집
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• pp.356-356
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• 2010

In this paper, Poly silicon thin-film transistors (poly-Si TFTs) with employed the SPC (Solid phase crystallization) and ELA (Excimer laser annealing) methods on glass panel substrate are fabricated to investigate the electrical poperies. Poly-Si TFTs have recess-channel structure with formated source/drain regions by LPCVD n+ poly Si in low $650^{\circ}C$ temperature. the ELA-TFT show higher on/off current ratio and subthreshold swing than a-Si and SPC TFT that therefore, these results showed that the ELA-TFT might be beneficial for practical embedded TFT memory device application.

• 대한전자공학회논문지SD
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• 제38권12호
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• pp.25-35
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• 2001

복잡한 thin film transistor-liquid crystal display (TFT-LCD) array 회로의 전기적 특성을 분석하기 위해서는 PSPICE나 AIM-SPICE와 같은 회로 시뮬레이터를 사용하는 것이 필수적이다. 본 논문에서는 SPICE 시뮬레이션을 위한 다결정 실리콘 (poly-Si) TFT 소자의 입력 변수 추출을 체계화하는 방법을 도입한다. 이 방법을 excimer laser annealing 및 silicide mediated crystallization 방법으로 각각 제작된 다결정 실리콘 TFT 소자에 적용하여 실험 결과와 잘 일치하는 결과를 얻었다. SPICE 시뮬레이터 중에서 PSPICE는 graphic user interface(GUI) 방식의 편의성을 제공하므로 손쉽게 복잡한 회로를 구성할 수가 있다는 장점이 있으나, poly-Si TFT 소자 모델을 가지고 있지 않다. 이 연구에서는 PSPICE에 다결정 실리콘 TFT 소자 모델을 이식하고, TFT가 이식된 PSPICE를 사용하여 poly-Si TFT-LCD 단위 화소 및 라인 RC 지연을 고려한 화소에 대한 전기적 특성을 분석하였다. 이러한 결과는 TFT-LCD 어레이 특성 분석을 위한 시뮬레이션을 효율적으로 수행하는데 기여할 수 있을 것으로 기대된다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.125-126
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• 2007

Polycrystalline silicon thin-film-transistors (Poly-Si TFT's) with a amorphous-$Si_xGe_y$ seed layer have been fabricated to improve the performance of TFT. The dependence of crystal structure and electrical characteristics on the the Ge fractions in $Si_xGe_y$ seed layer were investigated. As a result, the increase of grain size and enhancement of electrical characteristics were obtained from the poly-Si TFT's with amorphous-SixGey seed layer.

• 한국전기전자재료학회논문지
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• 제11권9호
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• pp.683-686
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• 1998

Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1998년도 추계학술대회 논문집
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• pp.141-144
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• 1998

The electrical characteristics of poly-Si TFT's with offset structure by negative bias stress are systematically investigated as a function of offset length. The changes of electrical characteristics, V$\_$th/, off-current, on/off ratio, in the offset structured poly-Si TFT's are smaller than that of the conventional structured poly-Si TFT's under the stress condition (V$\_$ds/=20V, V$\_$gs/=-20V). It is found that the hot carrier effect by negative bias stress is suppressed by the offset structured poly-Si TFT's because the local electric field near the drain region is decreased by offset region.

• 한국전기전자재료학회논문지
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• 제16권12호
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• pp.1065-1070
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• 2003

HTO(High Temperature Oxide) films are mainly used as a gate insulator for polysilicon thin film transistors(Poly-Si TFT's). The HTO films, however, show the demerits of a high leakage current and a low electric breakdown voltage comparing with conventional thermal oxides even though they have a better surface in roughness than the thermal oxides. In this paper, we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's. The leakage current and electric breakdown voltage of the ONO and HTO were measured. The drain current variation of poly-Si TFT's with a variety of gate insulators was observed. The thickness optimization in ONO films was carried out by studying I$\_$on/I$\_$off/ ratio of the poly-Si TFT's as a function of the thickness of ONO film adopted as gate insulator.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 1996년도 춘계학술대회 논문집
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• pp.90-93
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• 1996

The conduction mechanisms of the off-current in low temperature ($\leq$600$^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT's) has been systematically studied. Especially, the temperature and bias dependence of the off-current between unpassivated and passivated poly-Si TFT's was investigated and compared. The off-current of unpassivated poly-Si TFT's is due to a resistive current at low gate and drain voltage, thermal emission current at high gate, low drain voltage, and field enhanced thermal emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation, it was observed that the off-currents were remarkably reduced by plasma-hydrogenation. It was also observed that the off-currents of the passivated poly-Si TFT's are more critically dependent on temperature rather than electric field.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2001년도 하계종합학술대회 논문집(2)
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• pp.225-228
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• 2001

We simulated and analyzed the flicker phenomena in the poly-Si TFT-LCD using PSpice for the development of wide-area and high-quality LCD display We define the electric quantity of flicker in the TFT-LCD, which is the ratio of half frame frequency (30Hz) to DC (0 Hz) frequency. We compared two different types of TFTs, excimer laser annealed (ELA) poly-Si TFT and silicide mediated crystallization (SMC) poly-Si TFT, and found that the ELA and SMC TFTs show different flicker characteristics because of their mobility and leakage current. In addition, we showed that the gate voltage should be chosen carefully at the minimum flicker because of the larger leakage current of poly-Si Tn as compared with a-Si TFT

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2000년도 하계학술대회 논문집
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• pp.320-323
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• 2000

In the resent years, the Thin Film Transistor Liquid Crystal Display(TFT-LCD) have trend toward larger panel sizes and higher spatial and/or gray-scale resolution. In this trend, Because of its low field effect mobility, a-Si TFT is change to poly-Si TFT. In this paper, both effective-medium model of poly-Si TFTs and empirical capacitance model are applied to Pixel Design Array Simulation Tool (PDAST) and the pixel characteristics of TFT-LCD array were simulated, which were compared with the results calculated by Aim-Spice.

• 한국진공학회지
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• 제10권1호
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• pp.72-80
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• 2001

본 논문에서는 ELA(excimer laser annealing) 및 SMC(silicide mediated crystallization) 공정으로 제작된 다결정 실리콘 TFT-LCD(Thin Film Transistor-Liquid Crystal Display) 화소의 전기적 특성을 Spice회로 시뮬레이션을 통해 비교 분석하였다. 복잡한 TFT-LCD 어레이 (array) 회로의 전기적 특성 분석을 위하여 GUI(Graphic User Interface) 방식으로 손쉽게 복잡한 회로를 구성할 수 있는 PSpice에 AIM-Spice의 다결정 실리콘 박막 트랜지스터 소자 모델을 이식하고, AIM-Spice의 변수 추출법을 개선 체계화하였으며 ELA 및 SMC공정으로 각기 제작된 다결정 실리콘 박막트랜지스터에 적용하여 단위 화소 및 라인 RC 지연을 고려한 화소 특성을 비교 분석하였다. 비교 결과 ELA 다결정 실리콘 박막 트랜지스터 소자가 SMC에 비해 TFT-LCD의 화소 충전 시간 및 킥백(kickback) 전압 특성이 모두 우수하게 나타남을 확인하였다.