• Title/Summary/Keyword: poly-Si TFT

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Electrical properties of poly-Si TFT by crystallization method for embedded TFT memory application (임베다드 TFT 메모리 적용을 위한 결정화 방법에 따른 전기적 특성평가)

  • You, Hee-Wook;Cbo, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2010.06a
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    • pp.356-356
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    • 2010
  • In this paper, Poly silicon thin-film transistors (poly-Si TFTs) with employed the SPC (Solid phase crystallization) and ELA (Excimer laser annealing) methods on glass panel substrate are fabricated to investigate the electrical poperies. Poly-Si TFTs have recess-channel structure with formated source/drain regions by LPCVD n+ poly Si in low $650^{\circ}C$ temperature. the ELA-TFT show higher on/off current ratio and subthreshold swing than a-Si and SPC TFT that therefore, these results showed that the ELA-TFT might be beneficial for practical embedded TFT memory device application.

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A Systematic Method for SPICE Simulation of Electrical Characteristics of Poly-Si TFT-LCD Pixel (SPICE를 사용한 다결정 실리콘 TFT-LCD 화소의 전기적 특성 시뮬레이션 방법의 체계화)

  • Son, Myung-Sik;Ryu, Jae-Il;Shim, Seong-Yung;Jang, Jin;Yoo Keon-Ho
    • Journal of the Institute of Electronics Engineers of Korea SD
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    • v.38 no.12
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    • pp.25-35
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    • 2001
  • In order to analyze the electrical characteristics of complicated thin film transistor-liquid crystal display (TFT-LCD) array circuits, it is indispensible to use simulation programs such as PSPICE and AIM-SPICE. In this paper, we present a systematic method of extracting the input parameters of poly-Si TFT for SPICE simulations. This method was applied to two different types of poly-Si TFTs, fabricated by excimer laser annealing and silicide mediated crystallization methods, and yielded good fitting results to experimental data. Among the SPICE simulators, PSPICE has the graphic user interface feature making the composition of complicated circuits easier. We added successfully a poly-Si TFT device model to the PSPICE simulator, and analyzed easily the electrical characteristics of pixels considering the line RC delay. The results of this work would contribute to efficient simulations of poly-Si TFT-LCD arrays.

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Characterization of Poly-Si TFT's using Amorphous-$Si_xGe_y$ for Seed Layer (Amorphous-$Si_xGe_y$을 seed layer로 이용한 Poly-Si TFT의 특성)

  • Jung, Myung-Ho;Jung, Jong-Wan;Cho, Won-Ju
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2007.06a
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    • pp.125-126
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    • 2007
  • Polycrystalline silicon thin-film-transistors (Poly-Si TFT's) with a amorphous-$Si_xGe_y$ seed layer have been fabricated to improve the performance of TFT. The dependence of crystal structure and electrical characteristics on the the Ge fractions in $Si_xGe_y$ seed layer were investigated. As a result, the increase of grain size and enhancement of electrical characteristics were obtained from the poly-Si TFT's with amorphous-SixGey seed layer.

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A Study on the Hot-Carrier Effects of p-Channel Poly-Si TFT s (p-채널 Poly-Si TFT s 소자의 Hot-Carrier 효과에 관한 연구)

  • 진교원;박태성;백희원;이진민;조봉희;김영호
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.11 no.9
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    • pp.683-686
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    • 1998
  • Hot carrier effects as a function of bias stress time and bias stress consitions were syste-matically investigated in p-channel poly-Si TFT s fabricated on the quartz substrate. The device degradation was observed for the negative bias stress, while improvement of electrical characteristic except for subthreshold slope was observed for the positive bias stress. It was found that these results were related to the hot-carrier injection into the gate oxide and interface states at the poly-Si/$SiO_2$interface rather than defects states generation within the poly-Si active layer under bias stress.

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Negative Bias Stress Effect with Offset Structure in Poly-Si TFT's (Offset 구조 Poly-Si TFT의 Negative Bias Stress 효과)

  • 이제혁;변문기;임동규;조봉희;김영호
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1998.11a
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    • pp.141-144
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    • 1998
  • The electrical characteristics of poly-Si TFT's with offset structure by negative bias stress are systematically investigated as a function of offset length. The changes of electrical characteristics, V$\_$th/, off-current, on/off ratio, in the offset structured poly-Si TFT's are smaller than that of the conventional structured poly-Si TFT's under the stress condition (V$\_$ds/=20V, V$\_$gs/=-20V). It is found that the hot carrier effect by negative bias stress is suppressed by the offset structured poly-Si TFT's because the local electric field near the drain region is decreased by offset region.

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Properties of Poly-Si TFT's using Oxide-Nitride-Oxide Films as Gate Insulators (Oxide-Nitride-Oxide막을 게이트 절연막으로 사용하여 제조한 다결정실리콘 박막트랜지스티의 특성)

  • 이인찬;마대영
    • Journal of the Korean Institute of Electrical and Electronic Material Engineers
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    • v.16 no.12
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    • pp.1065-1070
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    • 2003
  • HTO(High Temperature Oxide) films are mainly used as a gate insulator for polysilicon thin film transistors(Poly-Si TFT's). The HTO films, however, show the demerits of a high leakage current and a low electric breakdown voltage comparing with conventional thermal oxides even though they have a better surface in roughness than the thermal oxides. In this paper, we propose an ONO(Oxide-Nitride-Oxide) multilayer as the gate insulator for poly-Si TFT's. The leakage current and electric breakdown voltage of the ONO and HTO were measured. The drain current variation of poly-Si TFT's with a variety of gate insulators was observed. The thickness optimization in ONO films was carried out by studying I$\_$on/I$\_$off/ ratio of the poly-Si TFT's as a function of the thickness of ONO film adopted as gate insulator.

Leakage Current Low-Temperature Processed Poly-Si TFT′s (저온제작 Poly-Si TFT′s의 누설전류)

  • 진교원;이진민;김동진;김영호
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 1996.05a
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    • pp.90-93
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    • 1996
  • The conduction mechanisms of the off-current in low temperature ($\leq$600$^{\circ}C$) processed polycrystalline silicon thin film transistors (LTP poly-Si TFT's) has been systematically studied. Especially, the temperature and bias dependence of the off-current between unpassivated and passivated poly-Si TFT's was investigated and compared. The off-current of unpassivated poly-Si TFT's is due to a resistive current at low gate and drain voltage, thermal emission current at high gate, low drain voltage, and field enhanced thermal emission current in the depletion region near the drain at high gate and drain voltage. After hydrogenation, it was observed that the off-currents were remarkably reduced by plasma-hydrogenation. It was also observed that the off-currents of the passivated poly-Si TFT's are more critically dependent on temperature rather than electric field.

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A Simulation Study on the Flicker Analysis for the Poly-Silicon TFT-LCD (다결정질 Si TFT-LCD에서의 Flicker에 대한 Simulation 연구)

  • 손명식;송민수;유건호;허지호;경희대학교물리학과;경희대학교물리학과
    • Proceedings of the IEEK Conference
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    • 2001.06b
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    • pp.225-228
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    • 2001
  • We simulated and analyzed the flicker phenomena in the poly-Si TFT-LCD using PSpice for the development of wide-area and high-quality LCD display We define the electric quantity of flicker in the TFT-LCD, which is the ratio of half frame frequency (30Hz) to DC (0 Hz) frequency. We compared two different types of TFTs, excimer laser annealed (ELA) poly-Si TFT and silicide mediated crystallization (SMC) poly-Si TFT, and found that the ELA and SMC TFTs show different flicker characteristics because of their mobility and leakage current. In addition, we showed that the gate voltage should be chosen carefully at the minimum flicker because of the larger leakage current of poly-Si Tn as compared with a-Si TFT

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Poly-Si TFT characteristic simulation by applying effective medium model (Effective Medium 모델 적용에 의한 poly-Si TFT 특성 Simulation)

  • 박재우;김태형;노원열;최종선
    • Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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    • 2000.07a
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    • pp.320-323
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    • 2000
  • In the resent years, the Thin Film Transistor Liquid Crystal Display(TFT-LCD) have trend toward larger panel sizes and higher spatial and/or gray-scale resolution. In this trend, Because of its low field effect mobility, a-Si TFT is change to poly-Si TFT. In this paper, both effective-medium model of poly-Si TFTs and empirical capacitance model are applied to Pixel Design Array Simulation Tool (PDAST) and the pixel characteristics of TFT-LCD array were simulated, which were compared with the results calculated by Aim-Spice.

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Comparative Pixel Characteristics of ELA and SMC poly-Si TETs for the Development of Wide-Area/High-Quality TFT-LCD (대화면/고화질 TFT-LCD 개발을 위하여 ELA 및 SMC로 제작된 다결정 실리콘 박막 트랜지스터의 화소 특성 비교)

    • Journal of the Korean Vacuum Society
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    • v.10 no.1
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    • pp.72-80
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    • 2001
  • In this paper, we present a systematic method of extracting the input parameters of poly-Si TFT(Thin-Film Transistor) for Spice simulations. This method has been applied to two different types of poly-Si TFTs such as ELA (Excimer Laser Annealing) and SMC (Silicide Mediated Crystallization) with good fitting results to experimental data. Among the Spice circuit simulators, the PSpice has the GUI(graphic user interface) feature making the composition of complicated circuits easier. We added successfully the poly-Si TFT model of AIM-Spice to the PSpice simulator, and analyzed easily to compare the electrical characteristics of pixels without or with the line RC delay. In the comparative results, the ELA poly-Si TFT is superior to the SMC poly-Si TFT in the charging time and the kickback voltage for the TFT-LCD (Thin Film Transistor-Liquid Crystal Display).

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