• Journal of the Korean Ceramic Society
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• v.36 no.6
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• pp.604-610
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• 1999

Silicide layer structures and morphology degradation of the surface and interface of the silicide layers for he Co/refractory metal bilayer sputter-deposited on the P-doped polycrystalline Si substrate and subjected to rapid thermal annealing were investigated and compared with those on the single Si substrate. The CoSi-CoSi2 phase transition temperature is lower an morphology degradation of the silcide layer occurs more severely for the Co/refractorymetal bilayer on the P-doped polycrystalline Si substrate than on the single Si substrate. Also the final layer structure and the morphology of the films after silicidation annealing was found to depend strongly upon the interlayer metal. The layer structure after silicidation annealing of Co/Hf/doped-poly Si is Co-Hf alloy/polycrystalline CoSi2/poly Si substrate while that of Co/Nb is polycrystalline CoSi2/NbSi2/polycrystalline CoSi2/poly Si.

• 한국정보디스플레이학회:학술대회논문집
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• 2003.07a
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• pp.630-633
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• 2003

Integrating the driver circuitry directly onto the glass substrate would be one of the advantages of polycrystalline Si (poly-Si) TFT-(LCD). Low-temperature poly-Si TFT(LTPS) is well-suited for higher-definition display applications due to its intrinsically superior electrical characteristics. In order to improve LTPS electrical characteristics, currently the excimer laser-induced crystallization (ELC) processes and sequential lateral solidification method were developed. Grain size of the poly-Si is mainly affected by beam pitch and energy density. Key parameter for making a larger poly-Si using excimer laser annealing(ELA) and increasing a throughput is due to increase in beam pitch and energy density to a certain degree. Furthermore, thin $SiO_{2}$ capping is effective to suppress the protrusion of the poly-Si thin films and to reduce the interface state density. From the ELA process, we are able to control grain size by varying different parameters such as number of shots and energy density.

• Proceedings of the Korean Vacuum Society Conference
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• 1999.07a
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• pp.70-70
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• 1999

현재 TFT-LCD에서 주류를 이루고 있는 a-Si 으로는 SXGA급 이상의 LCD를 구현하는 데 그 자체 이동도(0.4~1.0cm2/Vs)의 한계 때문에 poly-Si(100~300cm2/Vs)을 사용하지 않을 수 없다. Poly-Si을 성장시키는 방법으로는 PECVD 방법, SPC 방법, Laser Annealing 방법등이 있으나 아직 이 모든 방법으로는 성장박막의 질, 즉 이동도, 균일성 등이 만족스럽지 못하다. 그 중에서 Laser Annealing 방법으로 저온에서 가장 좋은 막질을 얻고 있으나 균일성 및 생산성 향상면에서 여려움이 제기되고 있다. 따라서 차세대 TFT-LCD의 핵심소재인 poly-Si을 저온에서 유리기판위에 양질의 박막으로 성장시킬 수 있는 박막성장법이 절실하다. 본 연구에서 사용된 실리콘 이온 증착법은 Sidl 이온 상태로 직접 증착되므로 이온 에너지가 직접 결합에 기여하게 되고 동시에 이온 에너지는 전기적으로 제어되므로 박막 형성에 필요한 정정 에너지를 공급할 수 있다. 따라서 종래의 열에너지만을 이용한 방법보다 훨씬 낮은 온도에서 박막을 성장시킬 수 있었다. 3kV의 Cs+에 의해 sputter 된 Si beam- 에너지를 20~100eV, Si- flux를 약 4$\mu$A.cm2로 조절하며, 기판온도 300~45$0^{\circ}C$에서 각각 제조하였다. 30$0^{\circ}C$, 20~50eV에서 poly-Si임을 XRD 분석으로 확인 할 수 있었다.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.14 no.2
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• pp.111-116
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• 2001

Poly-Si TFT's(Polysilicon thin filmtransistors) have been actively studied due to their applications in active matrix liquid crystal displays and active pull-up devices of CMOS SRAM's. For such applications, the leakage current has to be in the range of sub-picoampere. However, poly-Si TFT's suffer from anomalous high leakage currents, which is attributed to the emission of the traps present at gain boundaries in the drain junction. The leakage current has been analyzed by the field emission via grain-boundary traps and thermionic field emission over potential barrier located at the grain boundary. We found that the models proposed before are not consistent with the experimental results at far as drain-offset poly-Si TFT's we fabricated concern. In this paper, leakage current of drain-offset poly-Si TFT's with different offset lengths was studied. A conduction model based on the thermionic emission of the tunneling electrons is developed to identify the leakage mechanism. It was found that the effective grain size of the drain-offset region is important factor in the leakage current. A good agreement between experimental and simulated results of the leakage current is obtained.

• Journal of the Korean Vacuum Society
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• v.10 no.1
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• pp.72-80
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• 2001

In this paper, we present a systematic method of extracting the input parameters of poly-Si TFT(Thin-Film Transistor) for Spice simulations. This method has been applied to two different types of poly-Si TFTs such as ELA (Excimer Laser Annealing) and SMC (Silicide Mediated Crystallization) with good fitting results to experimental data. Among the Spice circuit simulators, the PSpice has the GUI(graphic user interface) feature making the composition of complicated circuits easier. We added successfully the poly-Si TFT model of AIM-Spice to the PSpice simulator, and analyzed easily to compare the electrical characteristics of pixels without or with the line RC delay. In the comparative results, the ELA poly-Si TFT is superior to the SMC poly-Si TFT in the charging time and the kickback voltage for the TFT-LCD (Thin Film Transistor-Liquid Crystal Display).

• Proceedings of the KIEE Conference
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• 2000.07c
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• pp.1772-1775
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• 2000

We have fabricated poly-Si TFTs by two-step crystallizaton. Poly-Si films have been prepared by furnace annealing(FA) and rapid thermal annealing(RTA) followed by subsequent the post-annealing, excimer laser annealing. The measured crystallinity of RTA and FA annealed poly-Si film is 77% and 68.5%, respectively. For two-step annealed poly-Si film, the crystallinity has been drastically to 87.7% and 86.3%. The RMS surface roughness from AFM results have been improved from 56.3${\AA}$ to 33.5${\AA}$ after post annealing. The measured transfer characteristics of the two-step annealed poly-Si TFTs have been improved significantly for the both FA-ELA and RTA-ELA. Leakage currents of two-step annealed poly-Si TFTs are lower than that of the devices by FA and RTA. From these results, we can describe the fact that the intra-grain defects has been cured drastically by the post-annealing.

• Journal of Information Display
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• v.2 no.2
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• pp.1-6
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• 2001

A $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with a new integrated 8-bit parallel-serial digital data driver was proposed and designed. For high resolution, the proposed parallel-serial digital driver used serial video data rather than parallel ones. Thus, digital circuits for driving one column line could be integrated within very small width. The parallel-serial digital data driver comprised of shift registers, latches, and serial digital-to-analog converters (DAC's). We designed a $1"{\times}l"$, $512{\times}512$ poly-Si TFT-LCD with integrated 8-bit parallel-serial digital data drivers by a circuit simulator which has physical-based analytical model of poly-Si TFT's. The fabricated shift register well operated at 2 MHz and $V_{DD}$=10V and the fabricated poly-Si TFT serial DAC's, which converts serial digital data to an analog signal, could convert one bit within $2.8{\mu}s$. The driver circuits for one data line occupied $8100{\times}50{\mu}m^2$ with $4{\mu}m$ design rule.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.28A no.12
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• pp.24-30
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• 1991

As a study to use Ti-silicides as interconnection material, the formation of Ti-silicides and the behavior of dopants were investigated for specimens where dopants are introduced on both single-Si substrate and poly-Si that was deposited on the single-Si. Result showed that stable C54 TiSiS12T formed above $700^{\circ}C$ and the formed TiSiS12T had bad surface roughness. And arsenics were chiefly redistributed in TiSiS12T while boron was accumulated near the interface between TiSiS11T and Si during RTA treatment.

• Proceedings of the KIEE Conference
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• 1995.07c
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• pp.1085-1087
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• 1995

A large leakage current may be one of the critical issues for poly-silicon thin film transistors(poly-Si TFTs) for LCD applications. In order to reduce the leakage current of poly-Si TFTs, several offset gated structures have been reported. However, those devices, where the offset length in the source region is not same as that in the drain region, exhibit the asymmetric electrical performances such as the threshold voltage shift and the variation of the subthreshold slope. The different offset length is caused by the additional mask step for the conventional offset structures. Also the self-aligned implantation may not be applicable due to the mis-alignment problem. In this paper, we propose a new fabrication method for poly-Si TFTs with a self-aligned offset gated structure by employing a photo resistor reflow process. Compared with the conventional poly-Si TFTs, the device is consist of two gate electrodes, of which one is the entitled main gate where the gate bias is employed and the other is the entitled subgate which is separate from both sides of the main gate. The poly-Si channel layer below the offset oxide is protected from the injected ion impurities for the source/drain implantation and acts as an offset region of the proposed device. The key feature of our new device is the offset lesion due to the offset oxide. Our experimental results show that the offset region, due to the photo resistor reflow process, has been successfully obtained in order to fabricate the offset gated poly-Si TFTs. The advantages of the proposed device are that the offset length in the source region is the same as that in the drain region because of the self-aligned implantation and the proposed device does not require any additional mask process step.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.52 no.6
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• pp.235-240
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• 2003

In this paper, we present the fabrication and the characteristic analysis of sequential lateral solidification(SLS) poly-Si thin film transistors(TFT's) with molybdenum gate for active matrix liquid displays (AMLCD's) pixel controlling devices. The molybdenum gate is applied for the purpose of low temperature processing. The maximum processing temperature is 55$0^{\circ}C$ at the dopant thermal annealing step. The SLS processed poly-Si film which is reduced grain and grain boundary effect, is applied for the purpose of electrical characteristics improvements of poly-Si TFT's. The fabricated low temperature SLS poly-Si TFT's had a varying the channel length and width from 10${\mu}{\textrm}{m}$ to 2${\mu}{\textrm}{m}$. And to analyze these devices, extract electrical characteristic parameters (field effect mobility, threshold voltage, subthreshold slope, on off current etc) from current-voltage transfer characteristics curve. The extract electrical characteristic of fabricated low temperature SLS poly-Si TFT's showed the mobility of 100~400cm$^2$/Vs, the off current of about 100pA, and the on/off current ratio of about $10^7$. Also, we observed that the change of grain boundary according to varying channel length is dominant for the change of electrical characteristics more than the change of grain boundary according to varying channel width. Hereby, we comprehend well the characteristics of SLS processed poly-Si TFT's witch is recrystallized to channel length direction.