• 한국전기전자재료학회논문지
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• 제25권11호
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• pp.857-861
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• 2012

FPN (fixed-pattern-noise) mainly comes from the device or pattern mismatches in pixel and color filter, pixel photodiode leakage in CMOS image sensor. In this paper, optical stack module related pixel FPN was investigated and the classification of pixel FPN contribution with the individual optical module process was presented. The methodology and procedure would be helpful in reducing the greater pixel FPN and distinguishing the complex FPN sources with respect to various noise factors.

• 한국방송∙미디어공학회:학술대회논문집
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• 한국방송∙미디어공학회 2022년도 하계학술대회
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• pp.1311-1314
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• 2022

DNN을 사용하여 객체 인식 과정에서 객체를 잘 분류하기 위해서는 시각적 설명성이 요구된다. 시각적 설명성은 object class에 대한 예측을 pixel-wise attribution으로 표현해 예측 근거를 해석하기 위해 제안되었다, Scale-invariant한 특징을 제공하도록 설계된 pyramidal features 기반 backbone 구조는 object detection 및 classification 등에서 널리 쓰이고 있으며, 이러한 특징을 갖는 feature pyramid를 trainable attention mechanism에 적용하고자 할 때 계산량 및 메모리의 복잡도가 증가하는 문제가 있다. 본 논문에서는 일반적인 FPN에서 객체 인식 성능과 설명성을 높이기 위한 피라미드-주의집중 계층네트워크 (FPN-Attention Layered Network) 방식을 제안하고, 실험적으로 그 특성을 평가하고자 한다. 기존의 FPN만을 사용하였을 때 객체 인식 과정에서 설명성을 향상시키는 방식이 객체 인식에 미치는 정도를 정량적으로 평가하였다. 제안된 모델의 적용을 통해 낮은 computing 오버헤드 수준에서 multi-level feature를 고려한 시각적 설명성을 개선시켜, 결괴적으로 객체 인식 성능을 향상 시킬 수 있음을 실험적으로 확인할 수 있었다.

• 센서학회지
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• 제14권3호
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• pp.191-197
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• 2005

When fabricating a vision chip, we should consider the noise problem, such as the fixed pattern noise(FPN) due to the process variation. In this paper, we propose an edge-detection circuit based on biological retina using the offset-free column readout circuit to reduce the FPN occurring in the photo-detector. The offset-free column readout circuit consists of one source follower, one capacitor and five transmission gates. As a result, it is simpler and smaller than a general correlated double sampling(CDS) circuit. A vision chip for edge detection has been designed and fabricated using $0.35\;{\mu}m$ 2-poly 4-metal CMOS technology, and its output characteristics have been investigated.

• 한국컴퓨터정보학회논문지
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• 제23권11호
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• pp.1-7
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• 2018

In this paper, we propose soft dead pixels detection method by analysing different response at hot and cold images. Abnormal pixels are able to effect detecting a small target. It also makes confusing real target or not cause of changing target size. Almost exist abnormal pixels after image signal processing even if dead pixels are removed by dead pixel compensation are called soft dead pixels. They are showed defect in final image. So removing or compensating dead pixels are very important for detecting object. The key idea of this proposed method, detecting dead pixels, is that most of soft deads have different response characteristics between hot image and cold image. General infrared cameras do NUC to remove FPN. Working 2-reference NUC must be needed getting data, hot & cold images. The way which is proposed dead pixel detection is that we compare response, NUC gain, at each pixel about two different temperature images and find out dead pixels if the pixels exceed threshold about average gain of around pixels.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2009년도 하계학술대회 논문집
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• pp.7-8
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• 2009

In the presence of infrared light, a CMOS Readout IC (ROIC) for a microbolometer typed infrared sensor detects the voltage or current that is caused by the changing in resistance in the bolometer sensor. A serious problem in designing the ROIC is how the value of the bolometer and reference resistors vary because of variations in manufacturing process. Since different pixel have different, resistance values, sensor operations must contend with fixed pattern noise (FPN) problems. In this paper, we propose a novel technique to compensate for the fluctuation in reference resistance by tiling into account the process variation. By using constant current source basing and correlated double sampling, we solved FPN.

• JSTS:Journal of Semiconductor Technology and Science
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• 제12권4호
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• pp.388-396
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• 2012

In this paper, a $320{\times}240$ pixel, 80 frame/s CMOS image sensor with a low power dual correlated double sampling (CDS) scheme is presented. A novel 8-bit hold-and-go counter in each column is proposed to obtain 10-bit resolution. Furthermore, dual CDS and a configurable counter scheme are also discussed to realize efficient power reduction. With these techniques, the digital counter consumes at least 43% and at most 61% less power compared with the column-counters type, and the frame rate is approximately 40% faster than the double memory type due to a partial pipeline structure without additional memories. The prototype sensor was fabricated in a Samsung $0.13{\mu}m$ 1P4M CMOS process and used a 4T APS with a pixel pitch of $2.25{\mu}m$. The measured column fixed pattern noise (FPN) is 0.10 LSB.

• 센서학회지
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• 제27권6호
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• pp.362-367
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• 2018

A complementary metal oxide semiconductor (CMOS) binary image sensor is proposed for low-power and low-noise operation. The proposed binary image sensor has the advantages of reduced power consumption and fixed pattern noise (FPN). A gate/body-tied (GBT) p-channel metal-oxide-semiconductor field-effect transistor (PMOSFET)-type photodetector is used as the proposed CMOS binary image sensor. The GBT PMOSFET-type photodetector has a floating gate that amplifies the photocurrent generated by incident light. Therefore, the sensitivity of the GBT PMOSFET-type photodetector is higher than that of other photodetectors. The proposed CMOS binary image sensor consists of a pixel array with $394(H){\times}250(V)$ pixels, scanners, bias circuits, and column parallel readout circuits for binary image processing. The proposed CMOS binary image sensor was analyzed by simulation. Using the dynamic comparator, a power consumption reduction of approximately 99.7% was achieved, and this performance was verified by the simulation by comparing the results with those of a two-stage comparator. Also, it was confirmed using simulation that the FPN of the proposed CMOS binary image sensor was successfully reduced by use of the double sampling process.

• 센서학회지
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• 제25권5호
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• pp.349-353
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• 2016

Recently, research on bolometer-type uncooled infrared image sensor which is made for industrial applications has been increasing. In general, it is difficult to calibrate fixed pattern noise (FPN) of bolometer array. In this paper, average-current calibration algorithm is presented for reducing bolometer resistance offset. A resistor which is produced by standard CMOS process, on the average, has a deviation. We compensate for deviation of each resistor using average-current calibration algorithm. The proposed algorithm has been implemented by a chip which is consisted of a bolometer pixel array, average current generators, current-to-voltage converters (IVCs), a digital-to-analog converter (DAC), and analog-to-digital converters (ADCs). These bolometer-resistor array and readout circuit were designed and manufactured by $0.35{\mu}m$ standard CMOS process.

• Smart Structures and Systems
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• 제29권1호
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• pp.153-166
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• 2022

Identifying fine cracks in steel bridge facilities is a challenging task of structural health monitoring (SHM). This study proposed an end-to-end crack image segmentation framework based on a one-step Convolutional Neural Network (CNN) for pixel-level object recognition with high accuracy. To particularly address the challenges arising from small object detection in complex background, efforts were made in loss function selection aiming at sample imbalance and module modification in order to improve the generalization ability on complicated images. Specifically, loss functions were compared among alternatives including the Binary Cross Entropy (BCE), Focal, Tversky and Dice loss, with the last three specialized for biased sample distribution. Structural modifications with dilated convolution, Spatial Pyramid Pooling (SPP) and Feature Pyramid Network (FPN) were also performed to form a new backbone termed CrackDet. Models of various loss functions and feature extraction modules were trained on crack images and tested on full-scale images collected on steel box girders. The CNN model incorporated the classic U-Net as its backbone, and Dice loss as its loss function achieved the highest mean Intersection-over-Union (mIoU) of 0.7571 on full-scale pictures. In contrast, the best performance on cropped crack images was achieved by integrating CrackDet with Dice loss at a mIoU of 0.7670.

• Journal of Electrical Engineering and Technology
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• 제7권2호
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• pp.221-224
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• 2012

We propose a Readout Integrated Circuit (ROIC), which applies a fixed current bias sensing method to the input stage in order to simplify the circuit structure and the infrared sensor characteristic control. For the sample-and-hold stage to display and control a signal detected by the infrared sensor using a two-dimensional (2D) focal plane array, a differential delta sampling (DDS) circuit is proposed, which effectively removes the FPN. In addition, the output characteristic is improved to have wider bandwidth and higher gain by applying a two-stage variable gain amplifier (VGA). The output characteristic of the proposed device was 23.91 mV/$^{\circ}C$, and the linearity error rate was less than 0.22%. After checking the performance of the ROIC using HSPICE simulation, the chip was manufactured and measured using the SMIC 0.35 um standard CMOS process to confirm that the simulation results from the actual design are in good agreement with the measurement results.