• Proceedings of the IEEK Conference
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• 2000.07a
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• pp.171-174
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• 2000

This paper proposes a pipelined adaptive filter based on affine projection algorithm with order 2. This filter gives a better convergence performance than that of LMS or NLMS pipeline algorithm and has same latency with the pipeline algorithm based on equivalent transformation. Compared to the critical path of the pipeline NLMS implementation, only 2 additions are increased in that of the proposed implementation.

• Journal of the Korea Society of Computer and Information
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• v.19 no.12
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• pp.133-141
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• 2014

An efficient method for reducing power consumption in pipelined deep packet inspection systems is proposed. It is based on the observation that the number of memory accesses is dominant for the power consumption and the number of accesses drops drastically as the input goes through stages of the pipelined AC-DFA. A DPI system is implemented where the operating frequency of the stages that are not frequently used in the pipeline is reduced to eliminate the waste of power consumption. The power consumption of the proposed DPI system is measured upon various input character set and up to 25% of reduction of total power consumption is obtained, compared to those of the recent DPI systems. The method can be easily applied to other pipelined architecture and string searching applications.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.20 no.5
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• pp.143-149
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• 2020

Currently, a multi-core processor is mainly used as a central processing unit of a computer system, and a high-performance out-of-order processor is adopted as each core to maximize system performance. The early out-of-order execution processor with Tomasulo algorithm aimed at floating-point instructions, and it took several cycles to execute by the use of complex structures such as reorder buffer and reservation station. However, in order for the processor to properly utilize out-of-order execution and increase the throughput of instructions, it must operate in a fully pipelined manner. In this paper, a fully pipelined out-of-order processor with speculative execution is designed with VHDL and verified with GHDL. As a result of the simulation, a program composed of ARM instructions is successfully performed.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.30 no.2A
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• pp.114-121
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• 2005

In this paper, Pipelined A/D converter with multi SHA structure is proposed for high speed operation. The proposed structure incorporates a multi SHA block that consists of multiple SHAs of identical characteristics in parallel to improve the conversion speed. The designed multi SHA is operated by non-overlapping clocks and the sampling speed can be improved by increasing the number of multiplexed SHAs. Pipelined A/D converter, applying the proposed structure, is designed to satisfy requirement of analog front-end of VDSL modem. The measured INL and DNL of designed A/D converter are $0.52LSB{\sim}-0.50LSB\;and\;0.80LSB{\sim}-0.76LSB$, respectively. It satisfies the design specifications for VDSL modems. The simulated SNR is about 66dB which corresponds to a 10.7 bit resolution. The power consumption is 24.32mW.

• The Transactions of the Korea Information Processing Society
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• v.2 no.4
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• pp.466-476
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• 1995

This pater describes pipelining algorithm issues for a VLIW(Very Long Instruction Word) System and the effective pipelined processing method by occurrence in pipelined management of processor minimized to timing delay. The proposed algorithm is executed in pipeline and parallel processings, and by combining basic operations variable instruction set can be desinged for various applications. In this paper, we prove and analyze the efficiency of the proposed pipeline algorithm and compare with other processor pipeline algorithm in terms of time minimizing.

• The Transactions of the Korea Information Processing Society
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• v.5 no.11
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• pp.2973-2979
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• 1998

As this paper is a scheduling algorithm for the synthesis of a pipelined datapath under resource constraints in high level synthesis, the proposed heuristic algorithm uses a priority function based on the collision count of resourecs. In order to schedule the pipelined datapath under resource constraints, we define the collision count and the priority function based on the collision count, a number of resource, and the mobility of operations to resolve a resource collision. The proposed algorithm supports chaining, multicycling, and structural pipelining to design the realistic hardware. The evaluation of the Performance is compared with other systems using the results of the synthesis for a 16point FIR filter and a 5th order elliptic wave filter, where in most cases, the optimal solution is obtained.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.8
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• pp.125-136
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• 2009

This paper presents a high-speed low-complexity two-bit level pipelined Viterbi decoder architecture for MB-OFDM UWB systems. As the add-compare-select unit (ACSU) is the main bottleneck of the Viterbi decoder, this paper proposes a novel two-bit level pipelined MSB-first ACSU, which is based on 2-step look-ahead techniques to reduce the critical path. The proposed ACSU architecture requires approximately 12% fewer gate counts and 9% faster speed than the conventional MSB-first ACSU. The proposed Viterbi decoder was implemented with $0.18-{\mu}m$ CMOS standard cell technology and a supply voltage of 1.8V. It operates at a clock frequency of 870 MHZ and has a throughput of 1.74 Gb/s.

• Journal of KIISE:Computer Systems and Theory
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• v.29 no.1
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• pp.10-15
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• 2002

This paper proposes the Pipelined Broadcast that broadcasts a message of size m in O(m+n-1) time in an n-dimensional hypercube. It is based on the replication tree, which is derived from the reachable sets. It greatly improves the performance compared to Ho-Kao s algorithm with the time of O(m[n/log(n+1)]). The communication in the broadcast uses all-port wormhole router with message replication capability. This paper includes the algorithm together with performance comparisons to previous schemes in practical implementation.

• Journal of Korea Multimedia Society
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• v.7 no.8
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• pp.1170-1182
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• 2004

A novel 4-way pipelined processing architecture is presented for three-step search block-matching motion estimation. For the 4-way pipelined processing, we have developed a method which divides the current block and search area into 4 subregions respectively and processes them concurrently. Also, we have developed memory partitioning method to access pixel data from 4 subregions concurrently without memory conflict. The architecture has been designed and simulated with C language and VHDL. Experimental results show that the proposed architecture achieves a high performance for real time motion estimation.

• The Transactions of the Korea Information Processing Society
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• v.2 no.2
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• pp.254-263
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• 1995

In this paper we discuss Moore and Mealy-model Time-stationary control schemes of pipelined data paths of Application Specific, Integrated Circuits (ASICs). We developed a method to synthesize both a Moore and a Mealy-style Finite State Machine(FSM) controller specifications given a pipelined data path with conditional branches. The control synthesis task consists of the generation of control specification and the FSM synthesis. The control specification procedure generates a FSM specification in the form of a state table. The different partitioning schemes are applied to each FSM controller so as to minimize the total area. Experimental results show the characteristics of the two different control styles and the effects of these two models on cost and performance.