• The Journal of Korean Institute of Communications and Information Sciences
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• v.37B no.9
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• pp.795-805
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• 2012

This paper proposes an algorithm and a hardware architecture for a broadcast communication which has the worst bottleneck among multiprocessor using distributed memory architectures. In conventional system, The pipelined broadcast algorithm is an algorithm which takes advantage of maximum bandwidth of communication bus. But unnecessary synchronization process are repeated, because the pipelined broadcast sends the data divided into many parts. In this paper, the MPI unit for pipeline chain algorithm based on circuit switching removing the redundancy of synchronization process was designed, the proposed architecture was evaluated by modeling it with systemC. Consequently, the performance of the proposed architecture was highly improved for broadcast communication up to 3.3 times that of systems using conventional pipelined broadcast algorithm, it can almost take advantage of the maximum bandwidth of transmission bus. Then, it was implemented with VerilogHDL, synthesized with TSMC 0.18um library and implemented into a chip. The area of synthesis results occupied 4,700 gates(2 input NAND gate) and utilization of total area is 2.4%. The proposed architecture achieves improvement in total performance of MPSoC occupying relatively small area.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.37 no.2
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• pp.37-42
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• 2000

In this paper, The high-speed, low-Power analog-to-digital conversion structure is proposed using the pipelined comparator away for high-speed conversion rate and the successive- approximation structure for low-power consumption. This structure is the successive-approximation structure using pipelined comparator array to change the reference voltage during the holding time. An 8-bit 10MS/s analog-to-digital converter is designed using 0.8${\mu}{\textrm}{m}$ CMOS technology. The INL/DNL errors are $\pm$0.5/$\pm$1, respectively. The SNR is 41㏈ at a sampling rate of 10MHz with 100KHz sine input signal. The Power consumption is 4.14㎽ at 10MS/s.

• The KIPS Transactions:PartA
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• v.9A no.3
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• pp.379-386
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• 2002

This paper presents a scheduling approach for synthesizing pipelined datapaths under resource constraints. Our approach builds up a schedule based on gradual mobility reduction in contrast to other algorithms of previous researches, where an operation being scheduled is selected by using a priority function. The proposed method consists of a scheduling algorithm and a decision algorithm for detecting any violation against resource constraints. Our approach evaluates whether or not a scheduling solution can exist in case an operation temporarily is assigned to the earliest or latest control step among the assignable steps for the operation. If a solution cannot be found, it is impossible to assign the operation to that step due to a violation against resource constraints, and so we can eliminate that control step. This process is iterated until a reduction of mobility for all operations can not be obtained. Experiments on benchmarks show that this approach gains a considerable improvement over those by previous approaches.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.11
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• pp.16-23
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• 2009

A 12b 10MS/s pipelined ADC with low DC gain amplifiers is presented. The pipelined ADC using a reference scaling technique is proposed to compensate the gain error in MDACs due to a low DC gain amplifier. To minimize the performance degradation of the ADC due to amplifier offset, the proposed offset trimming circuit is employed m the first-stage MDAC amplifier. Additional reset switches are used in all MDACs to reduce the memory effect caused by the low DC gain amplifier. The measured differential and integral non-linearities of the prototype ADC with 45dB DC gain amplifiers are less than 0.7LSB and 3.1LSB, respectively. The prototype ADC is fabricated in a $0.35{\mu}m$ CMOS process and achieves 62dB SNDR and 72dB SFDR with 2.4V supply and 10MHz sampling frequency while consuming 19mW power.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.4
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• pp.104-111
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• 2002

In this paper, we proposed the architecture of the decoder which implements the multi-view images decoding algorithm. The study of the hardware structure of the multi-view image processing has not been accomplished. The proposed multi-view images decoder operates in a three stage pipelined manner and extracts the depth of the pixels of the decoded image every clock. The multi-view images decoder consists of three modules, Node selector which transfers the value of the nodes repeatedly and Depth Extractor which extracts the depth of each pixel from the four values of the nodes and Affine transformer which generates the projecting position on the image plane from the values of the pixels and the specified viewpoint. The proposed architecture is designed and simulated by the Max+plus II design tool and the operating frequency is 30MHz. The image can be constructed in a real time by the decoder with the proposed architecture.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.11
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• pp.39-47
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• 1998

This paper describes high-speed pipelined memory architecture for a shared buffer ATM switch. The memory architecture provides high speed and scalability. It eliminates the restriction of memory cycle time in a shared buffer ATM switch. It provides versatile performance in a shared buffer ATM switch using its scalability. It consists of a 2-D array configuration of small memory banks. Increasing the array configuration enlarges the entire memory capacity. Maximum cycle time of the designed pipelined memory is 4 ns with 5 V V$\_$dd/ and 25$^{\circ}C$. It is embedded in the prototype chip of a shared scalable buffer ATM switch with 4 x 4 configuration of 4160-bit SRAM memory banks. It is integrated in 0.6 $\mu\textrm{m}$ 2-metal 1-poly CMOS technology.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.9 no.5
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• pp.1082-1088
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• 2005

Generating fast round key in AES Rijndael algorithm using three key sizes, such as 128, 192, and 256-bit keys is a critical factor to develop high throughput AES processors. In this paper, we propose on-the-fly round key generator which is applicable to the pipelined and non-pipelined AES processor in which cipher and decipher nodes must be implemented on a chip. The proposed round key generator has modular and area-and-time efficient structure implemented with simple connection of two key expander modules, such as key_exp_m and key_exp_s module. The round key generator for non-pipelined AES processor with support of three key lengths and cipher/decipher modes has about 7.8-ns delay time under 0.25um 2.5V CMOS standard cell library and consists of about 17,700 gates.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.6 no.5
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• pp.703-717
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• 2002

This paper illustrates the implementation of a scalable shared buffer asynchronous transfer mode (ATM) switch. The designed shared buffer ATM switch has a shared buffet of a pipelined memory which has the access time of 4 ns. The high-speed buffer access time supports a possibility of the implementation of a shared buffer ATM switch which has a large switching capacity. The designed switch architecture provides flexible switching performance and port size scalability with the independence of queue address control from buffer memory control. The switch size and the buffer size of the designed ATM switch can be reconfigured without serious circuit redesign. The designed prototype chip has a shared buffer of 128-cell and 4 ${\times}$ 4 switch size. It is integrated in 0.6um, double-metal, and single-poly CMOS technology. It has 80MHz operating frequency and supports 640Mbps per port.

• Journal of the Korea Computer Industry Society
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• v.3 no.3
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• pp.391-406
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• 2002

In order to realize a practical VOD system, it is necessary for a high-capacity and cost-effective hierarchical VOD server based on tertiary storages such as DVD jukebox. In such a system, it is possible to transfer multiple streams to users by alternatively swapping DVDs using the fixed number of drives. But it takes a long time for loading DVD to a drive. In this paper, we propose a primitive pipelined loading mechanism for hiding the loading time to swap DVDs in a hierarchical VOD server based on DVD jukebox. We also propose a enhanced pipelined loading mechanism for increasing the maximum admittable streams with the fixed number of drives. The enhanced mechanism caches the initial segment of each stream on a disk storage allowing faster data transfer. The performance analysis shows that the proposed mechanisms can admit the maximum allowed stream capacity under the fixed number of disk drives.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.12 no.6
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• pp.1026-1031
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• 2008

Nowdays, homes and small businesses rely more and more PON(Passive Optical Networks) for financial transactions, private communications and even telemedicine. Thus, encryption for these data transactions is very essential due to the multicast nature of the PON In this parer, we presented our implementation of a counter mode AES based on Virtex4 FPGA. Our design exploits three advanced features; 1) Composite field arithmetic SubByte, 2) efficient MixColumn transformation 3) and on-the-fly key-scheduling for fully pipelined architecture. By pipeling the composite field implementation of the S-box, the area cost is reduced to average 17 percent. By designing the on-the-fly key-scheduling, we implemented an efficient key-expander module which is specialized for a pipelined architecture.