• Journal of the Korea Society of Computer and Information
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• v.15 no.1
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• pp.13-21
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• 2010

IEEE 1149.1 test architecture was proposed to support the test of elements within the boards. It is a large serial shift register that uses the TDI pin as an input and the TDO pin as an output. Even though it performs the board level test perfectly, there is a problems of running system level test when the boards are equipped to the system. To test real time operation signal on test pin, output speed of serial shift register chain must be above double clock speed of shift register. In this paper, we designed a runtime test architecture and a runtime test procedure under running system environments to capture runtime signal at system clock rate. The suggested runtime test architecture are simulated by Altera Max+Plus 10.0. through the runtime test procedure. The simulation results show that operations of the suggested runtime test architecture are very accurate.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2003.06a
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• pp.1705-1708
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• 2003

The purpose of this study is to investigate the manufacturing technique on the U type Draw-Bending of inner grooved tube. This bending process make the U shape tube by Hair Pin Bending machine. The U type tube requires the quality of product that satisfy sufficient conditions for a heat exchanger. The mandrel components act the important roles that prevent wrinkles and keep the shape of cross section of bended tube at bending process. We performed the FEM simulation using LS-DYNA software and the bending test of inner groove tube and then, compared bending simulation with bending test results about mandrel ball diameter, mandrel position and optimal clearance between mandrel and tube.

• Nuclear Engineering and Technology
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• v.53 no.3
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• pp.932-941
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• 2021

This paper suggests a fracture simulation method for SFR metallic fuel pin under accident condition. Two major failure mechanisms - creep damage and eutectic penetration - are implemented in the suggested method. To simulate damaged element, stress-reduction concept to reduce stiffness of the damaged element is applied. Using the proposed method, the failure size of cladding can be predicted in addition to the failure time and failure site. To verify the suggested method, Whole-pin furnace (WPF) test and TREAT-M test conducted at Argonne National Laboratory (ANL) are simulated. In all cases, predicted results and experimental results are overall in good agreement. Based on the simulation result, the effect of eutectic-penetration depth representing failure behavior on failure size is studied.

• Journal of the Semiconductor & Display Technology
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• v.23 no.1
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• pp.97-103
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• 2024

In this paper, the difference between the S-parameter and the characteristic impedance according to the structural change of the fine pitch coaxial socket was analyzed. A pitch of the probe pin was applied to 0.20mm, and ground pins of different conditions were placed on each of the five signal pins. Insertion loss and reflection loss were analyzed for the coaxial socket of normal structure and the two sockets of the proposed structure. In addition, the difference in characteristic impedance was analyzed using time domain reflectometry. Through the analysis, it was confirmed that the characteristic impedance was improved applying the new structures of the socket at the same pitch

• Proceedings of the KIEE Conference
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• 2000.11d
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• pp.754-757
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• 2000

Si PIN diodes are subject to be damaged from the exposure of fast neutron by displacement of Si lattice structure. The defects are effective recombination centers for carriers which migrate through the base region of the PIN diode when forward voltage is applied. It causes an increase in current and a decrease in resistivity of the diode. This paper presents the development of a neutron sensor based on displacement damage effect. PIN diodes having various structures were made by micro-fabrication process, and neutron beam test was performed to identify neutron damage effect to the diode. From a result of the test, it was shown that the forward voltage drop of the diode, at a constant current, has good linearity for neutron dosage. Also it was found that the newton dosage can be measured by the pin diode neutron dosimeter with constant current power.

• The Transactions of the Korea Information Processing Society
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• v.1 no.3
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• pp.391-397
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• 1994

In this paper, we have developed a PLD Designer which is a design tool for digital circuits design using PLD device. PLD designer consists of a state graphic editor to extract boolean equations from state table within 20 states of FSM and a pin map editor to assign pin map for PLD device(PAL16R4, PAL22V10, GAL16V8, etc), which is suitable for extracted boolean equations. Also pin map editor generates a necessary JEDEC file to implement PLD device by using fuse map and checksum algorithm. To verify extracted boolean equation, we have developed simulation test vector generation algorithm. The results of JEDEC files generated by PLD designer is same with the results of JEDEC files generated by PALASM.

• Proceedings of the KIEE Conference
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• 2002.04a
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• pp.96-98
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• 2002

This paper proposes the digital pin line checker which can extremely improve the efficiency of the pine line checking using a micro processor. The line checker is designed which can check efficiently up to maximum 2048 pin. Alarm busser is designed ringing real-timely the case that the pin line is connected differently with real node number. Accordingly the comparing and identifying work visually the node number showing on the displaying board with real node number is avoided after the electronic stimulus enforce to the pin of the fixture by the test engineer. The digital line checker is designed based on the 8051. And the effectiveness and accuracy of the proposed line checking strategy is tested by simulating the several error connections for pin lines on the small scale board.

• Proceedings of the KSME Conference
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• 2004.04a
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• pp.7-12
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• 2004

Large-sized pins are usually used to lift and handle large low speed diesel engine crankshaft. There has then been a need to reduce and optimize the weight of the traditionally used pins. Making an hole by cutting the inside of the pin out was investigated in view of static and fracture strength. To compensate the stress increase caused by the introduction of the inner hole, the groove in the circumferential direction pre-existing on the pin is to be removed. Finite element analysis was carried out for both the original model and weight reduced model. Stress intensity factors for semi-elliptical defects assumed on the pin for the original model and weight reduced model was calculated using the ASME method and compared with the fracture toughness test result of the pin material. The diameter of the cutting hole for the revised model was determined based on the analysis results.

• Journal of the korean Society of Automotive Engineers
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• v.14 no.2
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• pp.110-119
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• 1992

Crank pin temperatures were measured and analyzed to find out practical method which can predict the engine bearing reliability. The measuring points were determined to be near the MOFT region and far from that by theoretical calculation. The effect of engine running condition, oil temperature, the change of oil circuit into bearing and crankshaft endplay on crank pin temperature were experimentally tested. The result obtained was as following. The crank pin temperature was dependent on oil film thickness and directly influenced by the change of test condition. Also, the length of the crankshaft endplay was confirmed to be critical to connecting rod bearing failure. In conclusion, we found that the measurement method of crank pin temperature can be used for predicting the engine bearing reliability.

• Journal of the Semiconductor & Display Technology
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• v.5 no.1 s.14
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• pp.33-38
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• 2006

The ATE driver to test a high speed semiconductor chip is designed by using general logic drivers instead of dedicated pin drivers. We have proposed a structure of general logic drivers using FPCA and assured its correct operation by EDA tool simulation. PCB circuit was implemented and Altera FPGA chip was programmed using DDR I/O library. On the PCB, it is necessary to place two resistors connected output drivers near to the output pin to adjust an impedance matching. We confirmed that the measured results agree with the simulated values within 5% errors at room temperature for the input signals with 800Mbps data transfer rate and 1.8V operating voltage.