• 한국진공학회지
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• 제7권s1호
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• pp.167-170
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• 1998

To apply diamond films in microelectromechanical systems(MEMS), it is necessary to develop the patterning technologies of diamond films in the micrometer scale. In this paper, three different kinds of technologies for patterning CVD diamond films carried out by us were demonstrated: selective growth by improved diamond nucleation in DC bias-enhanced microwave plasma chemical vapor deposition (MPCVD) system, selective growth of seeding using diamond-particle-mixed photoresist, and selective etching of oxygen ion beam using Al as the mask. It was show that high selectivity and precise patterns had been achieved, and all the processes were compatible with IC process.

• Progress in Superconductivity
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• 제1권2호
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• pp.95-98
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• 2000

We have studied critical currents of $YBa_2Cu_3O_7$ step-edge junctions with different step orientations with respect to the major axes of $SrTiO_3$ (100) substrates. The junctions were prepared by pulsed laser deposition and argon ion milling with photoresist mask. We investigated current-voltage characteristics and critical current of the junctions as a function of the angle. The junction critical current showed an angle dependent modulation with maxima near 0 or 90 degree and minima near 45 and 135 degrees. The experimental results were analyzed based on the microstructure of the junction along the step and the d-wave symmetry of $YBa_2Cu_3O_7$ superconductor.

• Design & Manufacturing
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• 제12권1호
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• pp.47-51
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• 2018

As the IT industry rapidly progresses, the functions of electronic devices and display devices are integrated with high density, and the model is changed in a short period of time. To implement the integration technology, a uniform micro-pattern implementation technique to drive and control the product is required. The most important technology for the micro pattern generation is the exposure processing technology. Failure to implement the basic pattern in this process cannot satisfy the demands in the manufacturing field. In addition, the conventional exposure method of the mask method cannot cope with the small-scale production of various types of products, and it is not possible to implement a micro-pattern, so an alternative technology must be secured. In this study, the technology to implement the required micro-pattern in semiconductor processing is presented through the photolithography process and plasma etching.

• 마이크로전자및패키징학회지
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• 제16권4호
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• pp.33-39
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• 2009

마스크리스 리소그래피(maskless lithography)에 응용하기 위한 마이크로렌즈 어레이(microlens array, MLA)가 석영의 습식 식각과 UV 접착제(UV adhesive)의 코팅을 바탕으로 개발되었다. 제작된 MLA의 초점거리는 ${\sim}45\;{\mu}m$ 정도였으며, 집광되는 광선의 초점은 ${\sim}1\;{\mu}m$로 측정되었다. MLA를 통과하며 초점을 맺은 빔(beam)의 크기 및 세기가 charge coupled device (CCD) 카메라와 빔 프로파일러(beam profiler)를 이용하여 각각 측정되었으며, 일정한 세기의 점들이 초점면에서 고르게 관찰되었다. 초점거리는 코팅된 UV 접착제의 두께에 따라 변화하였으며, UV 접착제의 두께가 두꺼울수록 짧아지는 경향을 보였다. 일반적인 마스크 얼라이너(mask aligner)를 이용한 MLA의 UV 포커싱(UV focusing)이 감광막(photoresist, PR) 상에서 실시되었으며, MLA를 통과한 빛이 감광막 위에 일정하게 집광되었다. 마스크 얼라이너와 MLA 사이의 거리 변화에 따라 감광막에 구현된 패턴 사이즈가 조절 되었다. 고온에서 오랜 시간이 지난 후에도 소자의 특성은 전혀 변함이 없었다.

• 한국진공학회:학술대회논문집
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• 한국진공학회 2012년도 제42회 동계 정기 학술대회 초록집
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• pp.431-432
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• 2012

In the era of 20 nm scaled semiconductor volume manufacturing, Microelectronics Manufacturing Engineering Education is presented in this paper. The purpose of microelectronic engineering education is to educate engineers to work in the semiconductor industry; it is therefore should be considered even before than technology development. Three Microelectronics Manufacturing Engineering related courses are introduced, and how undergraduate students acquired hands-on experience on Microelectronics fabrication and manufacturing. Conventionally employed wire bonding was recognized as not only an additional parasitic source in high-frequency mobile applications due to the increased inductance caused from the wiring loop, but also a huddle for minimizing IC packaging footprint. To alleviate the concerns, chip bumping technologies such as flip chip bumping and pillar bumping have been suggested as promising chip assembly methods to provide high-density interconnects and lower signal propagation delay [1,2]. Aluminum as metal interconnecting material over the decades in integrated circuits (ICs) manufacturing has been rapidly replaced with copper in majority IC products. A single copper metal layer with various test patterns of lines and vias and $400{\mu}m$ by $400{\mu}m$ interconnected pads are formed. Mask M1 allows metal interconnection patterns on 4" wafers with AZ1512 positive tone photoresist, and Cu/TiN/Ti layers are wet etched in two steps. We employed WPR, a thick patternable negative photoresist, manufactured by JSR Corp., which is specifically developed as dielectric material for multi- chip packaging (MCP) and package-on-package (PoP). Spin-coating at 1,000 rpm, i-line UV exposure, and 1 hour curing at $110^{\circ}C$ allows about $25{\mu}m$ thick passivation layer before performing wafer level soldering. Conventional Si3N4 passivation between Cu and WPR layer using plasma CVD can be an optional. To practice the board level flip chip assembly, individual students draw their own fan-outs of 40 rectangle pads using Eagle CAD, a free PCB artwork EDA. Individuals then transfer the test circuitry on a blank CCFL board followed by Cu etching and solder mask processes. Negative dry film resist (DFR), Accimage$^{(R)}$, manufactured by Kolon Industries, Inc., was used for solder resist for ball grid array (BGA). We demonstrated how Microelectronics Manufacturing Engineering education has been performed by presenting brief intermediate by-product from undergraduate and graduate students. Microelectronics Manufacturing Engineering, once again, is to educating engineers to actively work in the area of semiconductor manufacturing. Through one semester senior level hands-on laboratory course, participating students will have clearer understanding on microelectronics manufacturing and realized the importance of manufacturing yield in practice.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2011년도 제42회 하계학술대회
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• pp.1702-1703
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• 2011

MEMS 소자의 Wafer level Package 관련하여 Deep cavity를 가진 Cap Wafer와 Polymer bonding 중 cavity 단차로 인한 Polymer Patterning 및 접합 불량의 어려움을 극복할 수 있는 새로운 공정 flow를 제안하였다. Cavity를 형성할 때 사용하는 Si deep etching Mask인 기존의 Photoresist를 접합용 감광성 Polymer로 대체하고, cavity 형성 후, 별도의 추가 공정 없이 이 Polymer를 이용해 Wafer bonding을 진행하였다. 이를 통해 cavity 단차에 따른 문제를 해결함과 동시에 공정이 단순하고 제작 비용이 저렴하며, 신뢰성 있는 Wafer level Package를 구현하였다.

• 한국전기전자재료학회논문지
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• 제25권5호
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• pp.353-360
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• 2012

As semiconductor device technology continuously shrinks, low-open area etch process prevails in front-end etch process, such as contact etch as well as one cylindrical storage (OCS) etch. To eliminate over loaded wafer processing test, it is commonly performed to emply diced small coupons at stage of initiative process development. In nominal etch condition, etch responses of whole wafer test and coupon test may be regarded to provide similar results; however, optical emission spectroscopy (OES) which is frequently utilize to monitor etch chemistry inside the chamber cannot be regarded as the same, especially etch mask is not the same material with wafer chuck. In this experiment, we compared OES data acquired from two cases of etch experiments; one with coupon etch tests mounted on photoresist coated wafer and the other with coupons only on the chuck. We observed different behaviors of OES data from the two sets of experiment, and the analytical results showed that careful investigation should be taken place in OES study, especially in coupon size etch.

• 한국초전도학회:학술대회논문집
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• 한국초전도학회 1999년도 High Temperature Superconductivity Vol.IX
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• pp.147-151
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• 1999

YBCO step-edge Josephson junction were fabricated on sapphire substrates. The steps were formed on R-plane sapphire substrates by using Ar ion milling with PR masks. The step angle was controlled in the wide range from 25$^{\circ}$ to 50$^{\circ}$ by adjusting both the Ar ion incident angle and the photoresist mask rotation angle relative to the incident Ar ion beam. CeO$_2$ buffer layer and in-situ YBa$_2Cu_3O_{7-{\delta}}$ (YBCO) thin films was deposited on the stepped R-plane sapphire substrates by pulsed laser deposition method. The YBCO film thickness was varied to obtain the ratio of film thickness to step height in the range from 0.5 to 1. The step edge junction exhibited RSJ-like behaviors with I$_cR_n$ product of 100 ${\sim}$ 300 ${\mu}$V, critical current density of 10$^3$ ${\sim}$ 10$^5$ A/ cm$^2$ at 77 K.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2004년도 추계학술대회 논문집 Vol.17
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• pp.147-150
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• 2004

Back gate가 있는 $SiO_2$ 기판에 SWCNT(Single Walled Carbon Nanotube) 분산액을 도포하여 SWCNT 네트워크를 형성하였다. 금선을 shadow mask로 사용하여 $10{\mu}m$ 간격의 2단자 금 전극을 열 증착을 통해 형성하였다. 현미경 포토리소그래피를 통하여 시료의 가장자리를 Photoresist로 남겨두어 시료 가장자리의 나노튜브를 통한 단락을 방지하였다. 전류-전압 특성, 게이트 특성과 온도 의존성은 DAQ(Data Aquisition) 보드와 Keithley 2400을 사용하여 측정하였고, Labview 기반 프로그램을 통해 제어하였다. 음의 게이트 전압에서의 저항 감소를 관측함으로써 네트워크 상태에서의 게이트 의존성이 P 형 반도체 성질을 보여줌을 알 수 있었으며, 온도가 올라감에 따라 저항이 지수 함수적으로 증가하는 것으로부터 네트워크의 온도 의존성이 금속성 온도 의존성을 가지는 것을 확인하였다.

• Applied Microscopy
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• 제42권4호
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• pp.207-211
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• 2012

We examined the electrical properties and microstructure of NiO produced using a sol-gel method and Ni nitrate hexahydrate ($Ni[NO_3]_2{\cdot}6H_2O$) to investigate if this NiO thin film can be used as an insulator layer for resistance random access memory (ReRAM) devices. It was found that as-prepared NiO film was polycrystalline and presented as the nonstoichiometric compound $Ni_{1+x}O$ with Ni interstitials (oxygen vacancies). Resistances-witching behavior was observed in the range of 0~2 V, and the low-resistance state and high-resistance state were clearly distinguishable (${\sim}10^3$ orders). It was also demonstrated that NiO could be patterned directly by KrF eximer laser irradiation using a shadow mask. NiO thin film fabricated by the sol-gel method does not require any photoresist or vacuum processes, and therefore has potential for application as an insulating layer in low-cost ReRAM devices.