• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.123-126
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• 2004

We have demonstrated the fabrication of patterned 3D photonic crystals by holographic lithography in conjunction with soft lithography. Holographic lithography created 3D ordered macroporous structures and soft lithography made tailored defects. Because the hard baked photoresist pattern possessed high resistance against the uncured photoresist solution and the refractive index did not change appreciably by hard baking, a crosslinked photoresist was used as a relief pattern for the holographic fabrication of patterned 3D photonic crystals. More complicated defect geometries might be easily obtained with more complicated patterns on PDMS stamps. Moreover, the present results might be used as templates for 3D PCs of highindex defects that can be exploited as optical waveguides and optical circuits.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2004.10a
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• pp.379-382
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• 2004

Abrasive jet machining (AJM) has a large number of parameters such as powder flow rate, air pressure, diameter of abrasive, stand off distance, material hardness and fracture toughness, etc. It is not easy matter to control those parameter. To achieve high accurate machining, in this study, Taguchi method was used to select process parameters. The objective of the optimization was to get higher material removal rate (MRR). From the experiments and analysis, some process parameters were found to make efficient machining.

• Proceedings of the Materials Research Society of Korea Conference
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• 2003.03a
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• pp.126-126
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• 2003

유기트랜지스터에 관한 연구는 1980년 이후부터 시작되었으나 근래에 들어 전 세계적으로 본격적인 연구가 진행되고 있다. 제작공정이 간단하고 비용이 저렴하며 충격에 의해 깨지지 않고 구부리거나 접을 수 있는 전자 회로 기판이 미래의 산업에 필수적인 요소가 될 것으로 예상되고 있으며 이러한 요구를 충족시킬 수 있는 유기트랜지스터의 개발은 아주 중요한 연구분야로 대두되고 있다. 본 연구에서는 표면처리에 따른 contact angle, I-V 특성곡선, 표면 morphology 등의 결과로부터 dry cleaning 한 것이 wet cleaning한 것보다 왜 좋은지를 논하고자 한다. 먼저 N-type SiO$_2$ 기판을 이용하여 back면의 oxide층을 제거한 후, back gate용으로 사용하기 위하여 sputtering장치로 Au/Cr을 증차하였다. 그리고 기판에 앞면을 photolithography 공정을 이용하여 Au/Cr를 1000$\AA$ 증착 하여 source-, drain-eldctrode를 제조하였다. 그리고 SiO$_2$ 기판의 표면처리를 달리하여 그 위에 유기박막을 증착하여 특성을 비교하였다.

• Proceedings of the KAIS Fall Conference
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• 2002.05a
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• pp.106-108
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• 2002

반도체 physical layout design rule이 작아짐에 따라 Proximity effect와 overlay가 Pattern 구현에 크게 영향을 미치고 있다. Metal layer와 contact의 부족한 overlay margin으로 overlay 불량이 발생하고, 감소한 space margin으로 인해 bridge와 같은 문제가 나타난다. 따라서, resolution을 향상시키고, 최소한의 overlay margin을 확보함으로써 미세 pattern의 구현을 가능하게 한다. 이를 위해 OPC와 attPSM 같은 분해능향상기술이 사용된다. 그러나 attPSM의 사용은 원하지 않는 pattern이 생성되는 sidelobe와 같은 문제가 발생한다. 따라서 serial image simulation올 통해 추출한 rule을 rule-based correction에 적용하여 sidelobe현상을 방지한다. 그리고 overlay margin 부족으로 나타나는 문제는 metal layer와 contact overlap되는 영역의 line edge를 확장하고, rule checking을 통해 최소한의 space margin을 확보하여 해결한다 따라서 overlay error를 rule-based correction을 사용하여 효과적으로 방지한다.

• Journal of Microbiology and Biotechnology
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• v.16 no.8
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• pp.1216-1221
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• 2006

A protein array was fabricated for a miniaturized immunoassay using microcontact printing ($\mu$CP). A polydimethylsiloxane (PDMS) stamp with a 5 $\mu$m$\times$5 /$\mu$m dimension was molded from a silicon master developed by photolithography. Under optimal fabrication conditions, including the baking, incubation, and exposure time, a silicon master was successfully fabricated with a definite aspect ratio. An antibody fragment was utilized as the ink for the $\mu$CP, and transferred to an Au substrate because of the Au-thiol (-SH) interaction. The immobilization and antibody-antigen interaction were investigated with fluorescence microscopy. When human serum albumin (HSA) was applied to the protein array fabricated with an antibody against HSA, the detection limit was 100 pg/ml of HSA when using a secondary antibody labeled with a fluorescence tag. The fabricated protein array maintained its activity for 14 days.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1364-1367
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• 2007

In this study, the effect of binder polymer on the photolithographic patterning of barrier ribs was studied from view point of polymer structure and barrier rib pattern.

• 한국정보디스플레이학회:학술대회논문집
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• 2007.08b
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• pp.1249-1252
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• 2007

We have fabricated 3.5” transparent AM-OLED panel driven by PEALD grown ZnO TFT. The performance of ZnO thin film transistor was improved by adapting top gate structure, protection layer for ZnO from photolithography process, optimizing temperature and plasma power of ZnO growth process. The ZnO-TFT has a mobility of $8.9cm^2/V.s$, a subthreshold swing of 0.95V, and an on/off ratio of $10^7$.

• KIEE International Transactions on Electrophysics and Applications
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• v.11C no.2
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• pp.23-27
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• 2001

Microarray-based DNA chips provide an architecture for multi-analyte sensing. In this paper, we report a new approach for DNA chip microarray fabrication. Multifunctional DNA chip microarrays were made by immobilizing many kinds if DNAs on transducers (particles). DNA chip microarrays were prepared by randomly distributing a mixture of the particles on a chip pattern containing thousands of micro meter-scale sites. The particles occupied different sites from array to array. Each particle cam be distinguished by a tag that is established on the particle. The particles were arranged on the chip pattern by the random fluidic self-assembly (RFSA) method, using hydrophobic interaction.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2006.11a
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• pp.66-66
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• 2006

Development of ArF Photo-lithography process has proceeded with the increase of numerical aperature (NA) and the decrease of resist thickness. It makes many problems such as cost and process complexity. A novel spin-on hard mask system is proposed to overcome many problems Spin-on hard mask composed of two layers of siloxane and carbon. The optical thickness of two layers is designed from reflectivity measurement at specified n, k respectively. The property of photo-resist shows different results according to Si contents. Si-contents was measured XPS(X-ray Photoelectron spectroscopy).

• Proceedings of the Korea Society for Simulation Conference
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• 2001.10a
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• pp.269-273
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• 2001

Semiconductor wafer fabrication is a business of high capital investment and fast changing nature. To be competitive, the production in a fab needs to be effectively planned and scheduled starting from the ramping up phase, so that the business goals such as on-time delivery, high output volume and effective use of capital intensive equipment can be achieved. In this paper, we propose Stand Alone layout and In-Line layout are analyzed and compared while varying number of device variable changes. The comparison is performed through simulation using ProSys; a window 98 based discrete system simulation software, as a tool for comparing performance of two proposed layouts. The comparison demonstrates that when the number of device variable change is small, In-Line layout is more efficient in terms of production quantity. However, as the number of device variable change is more than 14 titles, Stand Alone layout prevails over In-Line layout.