• Applied Chemistry for Engineering
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• v.24 no.6
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• pp.593-598
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• 2013

In this study, we have evaluated the water absorption phenomenon of photoresist dry film, which is commonly used to build circuits on PCB (Printed Circuit Board) by photolithography, by using ATR-FTIR (Attenuated Total Reflectance-Fourier Transform Infrared). We have firstly observed significant change in fracture mode of dry film with respect to temperature and humidity, which we assumed the material transition from ductile to brittle. Secondly, we have established the process of absorption test for determining the diffusion coefficients of water into the dry film both with gravimeter and ATR-FTIR. We have successfully calculated the diffusion coefficients for each environmental conditions from the results which we achieved by gravimeter and ATR-FTIR. Compared to the gravimeter which is a conventional method for absorption test, the ATR-FTIR method in this study has been found to be very easy to use and have the same accuracy as gravimeter. Moreover, we are expecting to use the ATR-FTIR as an appropriate method to study the absorption phenomena related to any kinds of solvent and polymer system.

• Journal of the Korean Crystal Growth and Crystal Technology
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• v.9 no.1
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• pp.60-63
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• 1999

Application of reactive ion etching (RIE) technique to Ta-Al alloy thin film with a thickness of $1000{\AA}$ was studied. $CF_{4}$ gas could be used effectively to etch the Ta-Al alloy thin film. The etching rate in the thin film with Ta content of 50 mol% was about $67{\AA}/min$. NO selectivity between the Ta-Al alloy film and $SiO_{2}$ film was observed during the etching using the $CF_{4}$ gas. The etching rate of the $SiO_{2}$ layer was 12 times faster than that of the Ta-Al alloy thin film. It was also observed that photoresist of AZ5214 was more useful than Shiepley 1400-27 in RIE with the $CF_{4}$ gas.

• Journal of the Korean Vacuum Society
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• v.6 no.2
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• pp.103-108
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• 1997

Silicon field emitter arrays (FEAs) have been fabricated by a novel method employing a two-step tip etch and a spin-on-glass (SOG) etch-back process using double layered thermal/tetraethylortho-silicate (TEOS) oxides as a gate dielectric. A partial etching was performed by coating a low viscous photo resist and $O_2$ plasma ashing on order to form the double layered gate dielectric. A small gate aperture with low gate leakage current was obtained by the novel process. The hight and the end radius of the fabricated emitter was about 1.1 $\mu\textrm{m}$ and less than 100$\AA$, respectively. The anode emission current from a 256 tips array was turned-on at a gate voltage of 40 V. Also, the gate current was less than 0.1% of the anode current.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.12 no.4
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• pp.1993-1998
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• 2011

Semiconductor industry needs to have fine patterns in order to fabricate the high density integrated circuit. For nano-scale patterns, hard-mask is used to multi-layer structure which is formed by CVD (chemical vaporized deposition) process. In this work, we prepared single-layer hard-mask by using organic-inorganic hybrid polymer for spin-on process. The inorganic part of hard-mask was much easier etching than photo resist layer. Beside, the organic part of hard-mask was much harder etching than substrate layer. We characterized the optical and morphological properties to the hard mask films using organic-inorganic hybrid polymer, and then etch rate of photo resist layer and hard-mask film were compared. The hybrid polymer prepared from organic and inorganic materials was found to be useful hard-mask film to form the nano-patterns.

• Transactions on Electrical and Electronic Materials
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• v.16 no.4
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• pp.169-172
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• 2015

Although, there are several research studies on the engineering of the graphene layers using different etching techniques, there is not any comprehensive study on the effects of using different etching masks in the reactive ion etching (RIE) method on the quality and uniformity of the etched graphene films. This study investigated the effects of using polystyrene and conventional photolithography resist as a etching mask on the engineering of the number of graphene layers, using RIE. The effects were studied using Raman spectroscopy. This analysis indicated that the photo-resist mask is better than the polystyrene mask because of its lower post processing effects on the graphene surface during the RIE process. A single layer graphene was achieved from a bi-layer graphene after 3 s of the RIE process using oxygen plasma, and the bi-layer graphene was successfully etched after 6 s of the RIE process. The bilayer etching time was significantly smaller than reported values for graphene flakes in previous research.

• Polymer(Korea)
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• v.31 no.5
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• pp.442-446
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• 2007

Alkali soluble and photo-curable polyesters were prepared from fluorene epoxy acrylate and various aromatic dianhydrides. To make a black matrix for LCD color-filter application, photo-resist solution was made by mixing synthesized polyester as binder, carbon black as pigment, initiator and multifunctional monomer in solvent. Black matrix pattern was formed on the glass substrate by lithography process. In this study, we synthesized various polyester-based binder polymers for LCD color-filter applications, and compared the analytical properties of those polymers and lithography patterns.

• Proceedings of the Korean Vacuum Society Conference
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• 2010.02a
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• pp.84-84
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• 2010

In this study, we report on the novel lithographic patterning method to fabricate organic-semiconductor devices based on photo and e-beam lithography with well-known silicon technology. The method is applied to fabricate pentacene-based organic field effect transistors. Owing to their solubility, sub-micron sized patterning of P3HT and PEDOT has been well established via micromolding in capillaries (MIMIC) and inkjet printing techniques. Since the thermally deposited pentacene cannot be dissolved in solvents, other approach was done to fabricate pentacene FETs with a very short channel length (~30nm), or in-plane orientation of pentacene molecules by using nanometer-scale periodic groove patterns as an alignment layer for high-performance pentacene devices. Here, we introduce the atomic layer deposition of $Al_2O_3$ film on pentacene as a passivation layer. $Al_2O_3$ passivation layer on OTFTs has some advantages in preventing the penetration of water and oxygen and obtaining the long-term stability of electrical properties. AZ5214 and ma N-2402 were used as a photo and e-beam resist, respectively. A few micrometer sized lithography patterns were transferred by wet and dry etching processes. Finally, we fabricated sub-micron sized pentacene FETs and measured their electrical characteristics.

• Korean Chemical Engineering Research
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• v.54 no.1
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• pp.108-113
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• 2016

A miniaturized lab-scale Cu plating cell for the metallization of electronic devices was fabricated and its deposit uniformity and profile were investigated. The plating cell was composed of a polypropylene bath, an electrolyte ejection nozzle which is connected to a circulation pump. In deposit uniformity evaluation, thicker deposit was found on the bottom and sides of substrate, indicating the spatial variation of deposit thickness was governed by the tertiary current distribution which is related to $Cu^{2+}$ transport. The surface morphology of Cu deposit inside photo-resist pattern was controlled by organic additives in the electrolyte as it led to the flatter top surface compared to convex surface which was observed in the deposit grown without organic additives.

• Proceedings of the KIEE Conference
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• 1992.07b
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• pp.850-853
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• 1992

A cryogenic electron cyclotron resonance plasma etching system has been built to study wafer-temperature in the silicon etching characteristics. The wafer temperature was controlled from -150 to +30 $^{\circ}C$ during etching using the liquid nitrogen cooled helium gas. Although silicon was etched isotropically in $SF_6$ plasma at room temperatures, we found that it is possible to suppress the etch undercut in Si by reducing a substrate temperature without side wall passivation. In addition, the selectivity of silicon to photoresist was improved considerably at a low wafer temperature. Etch rates, anisotropy and selectivity to photo resist are measured as a function of the wafer temperature in the region of -125 $\sim$ 25$^{\circ}C$ and rf bias power of 20W $\sim$ 80W.

• Journal of Institute of Convergence Technology
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• v.2 no.2
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• pp.25-29
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• 2012

Micro machining technologies have been required to satisfy various conditions in a high-technology industry. Micro electrochemical process is one of the most precision machining methods. Micro electrochemical process has been divided into electrochemical etching through protective layer and electrochemical machining using ultrashort voltage pulses. Micro shaft can be fabricated by electrochemical etching. The various protective layers such as photo-resist, oxide layer and oxidized recast layer have been used to protect metal surface during electrochemical etching. Micro patterning on metal surface can be machined by electrochemical etching through protective layer. Micro hole, groove and structures can be easily machined by electrochemical machining using ultrashort voltage pulses. Recently, the groove with subnanometer was machined using AFM.