• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.22 no.3
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• pp.399-405
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• 2011

In this paper, we present the design of Q-band LC VCO and injection locking buffer for 77 GHz automotive radar sensor using 130 nm RF CMOS process. To improve the phase noise characteristic of LC tank, the transmission line is used. The negative resistance by the active device cross-coupled pair of buffer is used for high output power, with or without oscillation of buffer. The measured phase noise is -102 dBc/Hz at 1 MHz offset frequency and tuning range is 34.53~35.07 GHz. The output power is higher than 4.1 dBm over entire tuning range. The fabricated chip size is $510{\times}130\;um^2$. The power consumption of LC VCO is 10.8 mW and injection locking buffer is 50.4 mW from 1.2 V supply.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 1995.09a
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• pp.45-45
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• 1995

• Proceedings of the Korean Magnestics Society Conference
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• 2017.05a
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• pp.164-164
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• 2017

• Proceedings of the IEEK Conference
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• 1999.06a
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• pp.978-981
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• 1999

In this paper, an improved integer-N frequency synthesizer that can be synthesized into smaller channel space than input signal frequency is presented. The proposed frequency synthesizer also has an characteristics of fast phase locking time. The frequency synthesizer performed in the manner that it divides various outputs of different phases in VCO by means of dividers that have different control signals respectively and then add the divided signal. In order to confirm the characteristics of proposed frequency synthesizer, behavioral and SPICE simulations are performed using C-language and HSPICE respectively.

• Proceedings of the KIEE Conference
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• 1987.11a
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• pp.86-89
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• 1987

This paper treats with the design and fabrication of a frequency synthesizer for the generation of intermediate frequency of a HF band transceiver. The synthesizer is designed to control frequencies using a phase-locked loop and it is shown that method improved the performance of frequency accuracy and locking time then that of the crystal-reference system.

• Proceedings of the KIEE Conference
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• 1997.11a
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• pp.456-458
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• 1997

The phase-lock technique is applied to a three-phase semi-bridge type battery charger system. Using an inner fast dynamic loop, the phase-locked voltage control (PLVC) technique of three-phase semi-bridge converter is proposed to give a frequency synchronism and to reduce the subharmonics due to the unbalance of transformer or power line. To protect the power devices, the two stage soft-start, function with softly locking the phase and softly increasing the current is presented. As limiting the reference voltage of the inner voltage control loop, muti-lock phenomena are removed on the PLVC loop. A current limit function is also proposed to limit the current of battery and converter. The proposed controller is confirmed through experiment results.

• Current Optics and Photonics
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• v.5 no.3
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• pp.289-297
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• 2021

We describe a comb-mode resolving spectroscopic technique by direct time-domain phase correction of unstable interferograms obtained from loosely locked two femtosecond lasers. A low-cost continuous wave laser and conventional repetition rate stabilization method were exploited for locking carrier and envelope phase of interferograms, respectively. We intentionally set the servo control at low bandwidth, resulting in severe interferograms' fluctuation to demonstrate the capability of the proposed correction method. The envelope phase of each interferogram was estimated by a quadratic fit of carrier peaks to correct timing fluctuation of interferograms in the time domain. After envelope phase correction on individual interferograms, we successfully demonstrated 1 Hz linewidth of RF comb-mode over 200 GHz optical spectral-bandwidth with 10-times signal-to-noise ratio (SNR) enhancement compared to the spectrum without correction. Besides, the group delay difference between two femtosecond pulses is successfully estimated through a linear slope of phase information.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.4
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• pp.21-26
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• 2008

In this paper, a novel 622Mbps burst-mode clock and data recovery (CDR) circuit is proposed for passive optical network (PON) applications. The CDR circuits are implemented with 0.35um CMOS process technology. Locking dynamics is accomplished with instantaneous feature and data are sampled at an optimal timing. This is realized by seven different delay configurations, which are generated from precisely-controlled delay buffers. The experimental results show that the proposed CDR circuits are operating as expected, recovering an incoming 622Mbps burst-mode input data without errors.

• The Transactions of the Korean Institute of Electrical Engineers D
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• v.55 no.12
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• pp.526-533
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• 2006

In this paper, we presented the synchronization module between RF shower system and RFID Reader to extend interrogating range on Mobile RFID system, Costas Loop and FPLL(Frequency/phase Lock Loop) were used. We achieved compromised range of 3MHz locking frequency, 1ms locking time and figured out remarkable Hopping frequency of the Reader. The prototype of the new designed RFID system has been tested with ISO18000-6 type-B Tag. The read range between designed RFID Reader and Tag has been measured, it increased triple times by adjusting the Shower system output level.

• Proceedings of the Korea Information Processing Society Conference
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• 2004.05a
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• pp.105-108
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• 2004

다단계 보안데이터베이스 시스템에서 기본적인 병행수행 제어 기법들은 비밀채널과 교착상태등과 같은 문제들이 발생하였다. 이에 직렬화 순서를 동적으로 재조정함으로서 해결하려는 방안이 있었지만, 알고리즘의 복잡성으로 인해 오버 헤드와 많은 수행시간이 필요하게 되었고, 이에 따라 많은 양의 시스템 자원과 높은 사양의 시스템을 요구하게 되었다. 또한 이러한 방법은 다중 버전을 사용함으로서 추가적인 관리비용이 높게 되었고, 각각의 트랜잭션이 지연 및 재수행이란 불필요한 과정을 반복하게 되었다. 따라서 본 논문에서는 제안한 알고리즘은 데이터베이스의 용도에 맞게 직렬화 순서를 보장하여 스케줄을 관리하는 요청 2단계 로킹기법(Request Two-phase Locking)으로서 이는 2단계 로킹기법의 기본원리에 요청로크를 사용함으로 보다 효율적으로 병행제어를 할 수 있다. 여기서 요청로크는 각각의 트랜잭션 스케줄에 로크획득 및 해제를 병행수행제어의 필요에 따라 유동적으로 할 수 있으며, 읽기로크, 쓰기로크, 요청로크라는 3가지 로킹모드를 통해 대처방안을 마련함으로서, 충돌을 방지하며, 충돌연산의 특성에 따라 직렬화 순서를 동적으로 조정함으로 블록킹을 막는 병행제어를 응용하여 병렬성을 유지한다.