• Korean Journal of Optics and Photonics
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• v.4 no.3
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• pp.330-337
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• 1993

Figure '8' type, passively-mode-locked erbium-doped-fiber ring laser was developed, incorporating a nonlinear loop mirror. Transmittance of the loop mirror was found to be dependent on the incident light intensity due to the non-reciprocal nonlinear phase shift, which enables the passive mode locking of the laser. Self-starting of stable mode locking was possible with only controlling the polarization controllers inside the cavity without any help of external perturbation or modulation. The mode-locked output pulse shape was discussed in relation with the transmission characteristics of nonlinear loop mirror.

• Proceedings of the Korea Information Processing Society Conference
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• 2003.05c
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• pp.1511-1514
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• 2003

본 논문에서는 모바일 데이터베이스 시스템에서 동시성제어의 정도를 높이고자 새로운 프로토콜을 제안한다. 트랜잭션의 동시성제어를 하는데 있어서 다중적인 접근으로부터 문제시되는 데이터 일관성을 보장하고, 대역폭이 낮은 모바일 환경 속에서 일어날 수 있는 잦은 접속 단절과 잦은 이동에 대한 트랜잭션 처리의 효율을 높이고자 한다. 2PL(two-phase locking)로부터 확장된 프로토콜인 XAL(extended altruistic locking)모델의 연장으로서 양방향(Bi-directional) 기부연산에 따른 트랜잭션의 처리와 트랜잭션을 판독전용과 판독 및 갱신용 트랜잭션의 두 가지로 분류함으로서 이동 컴퓨터 환경에서 단기 트랜잭션의 처리성능의 정도를 높이고자 한다.

• Korean Journal of Optics and Photonics
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• v.5 no.2
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• pp.278-285
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• 1994

We investigated the spectral characteristics for temperature and driving current change in visible laser diode. As a result of spectrum analysis, the ratio of frequency change for temperature and driving current change were about $33 GHz/^{\circ}C$, 6.6 GHz/mA in the region which was not mode hopping range. Compared to the sharp mode hopping in the near IR single mode AlGaAs lasers, the visible laser diode showed relatively broad multimode operation in the mode hopping region. We performed the experiment of injection-locking characteristics analysis for visible laser diode. Locking half bandwidth(LHBW) was measured 0~5.0 GHz for $0~25\muW$ input power and it was dependent on the input power. Also, LHBW for polarization angle was dependent on the difference of polarization angle between master laser and slave laser. The phase change of injection-locked output beam of the slave laser diode as a function of the drive current was measured in the interferometer which was composed of master laser and slave laser. The ratio of phase change with the slope of 5.0~1.3 rad/mA was obtained within injection-locking range for the change of $2~25\muW$ input power. power.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2625-2628
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• 2003

Phase locked loops are widely used in many applications such as frequency synthesis, clock/data recovery and clock generation. In nearly all the PLL applications, low jitter and fast locking time is required. Without using adaptive loop filter, this paper proposes very simple method for improving locking time and jitter reduction simultaneously in charge pump PLL(CPPLL) using Daul Phase/Frequency Detector(Dual PFD). Based on the proposed scheme, the lock time is improved by 23.1％, and the jitter is reduced by 45.2％ compared with typical CPPLL.

• Journal of electromagnetic engineering and science
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• v.8 no.3
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• pp.134-137
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• 2008

This paper proposes a novel quadrature VCO(QVCO) based on direct back-gate second harmonic coupling. The QVCO directly couples the current sources of the conventional LC VCOs through the back-gate instead of front-gate to generate quadrature signals. By the second harmonic injection locking, the two LC VCOs can generate quadrature signals without using on-chip transformer, or stability problem that is inherent in the direct front-gate second harmonic coupling. The proposed QVCO is implemented in $0.18{\mu}m$ CMOS technology operating at 2 GHz with 5.0 mA core current consumption from 1.8 V power supply. The measured phase noise of the proposed QVCO is - 63 dBc/Hz at 10 kHz offset, -95 dBc/Hz at 100 kHz offset, and -116 dBc/Hz at 1 MHz offset from the 2 GHz output frequency, respectively. The calculated figure of merit(FOM) is about -174 dBc/Hz at 1 MHz offset. The measured image band rejection is 46 dB which corresponds to the phase error of $0.6^{\circ}$.

• ETRI Journal
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• v.18 no.3
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• pp.161-170
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• 1996

We show that the electrically coupled Hindmarsh-Rose neuronal model exhibits various patterns of phase locking at fixed parameter value. Through the analysis of the effective coupling, the system is shown to be stabilized in one of these patterns according to the initial conditions. This corresponds to the parameter-tuning independent mode-switching mechanism that changes the electrical output of neuronal systems. It is also presented how the stable fixed points of the effective coupling which characterize the phase locking patterns depend on the external current.

• Current Optics and Photonics
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• v.7 no.6
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• pp.708-713
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• 2023

A robust all-fiber nonlinear amplifying loop-mirror-based mode-locked femtosecond laser is demonstrated. Power-dependent nonlinear phase shift in a Sagnac loop enables stable and power-efficient mode-locking working as an artificial saturable absorber. The pump power is adjusted to achieve the lowest intensity noise for stable long-term operation. The minimum pump power for mode-locking is 180 mW, and the optimal pump power is 300 mW. The lowest integrated root-mean-square relative intensity noise of a free-running mode-locked laser is 0.009% [integration bandwidth: 1 Hz-10 MHz]. The long-term repetition-rate instability of a free-running mode-locked laser is 10^-7 over 1,000 s averaging time. The repetition-rate phase noise scaled at 10-GHz carrier is -122 dBc/Hz at 10 kHz Fourier frequency. The demonstrated method can be applied as a seed source in high-precision real-time mid-infrared molecular spectroscopy.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.90-96
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• 2006

A novel ${\Sigma}{\Delta}$ fractional-N PLL architecture for fast locking and fractional spur suppressing is proposed based on the capacitance scaling scheme. It changes the effective capacitance of loop filter (LF) by increasing and decreasing current to the capacitor via different paths with multiple charge pumps. The effective capacitance of loop filter (LF) can be scaled up/down depending on operating status while keeping LF capacitors small enough to be integrated into a single PLL chip. Fractional spurs suppressing have been achieved by reducing the magnitude of charge pump current when the PLL is in-lock without degrading fast locking characteristic. It has been simulated by HSPICE in a CMOS $0.35{\mu}m$ process, and shows flat locking time is less than $8{\mu}s$ with the small size of LF capacitors, 200pF and 17pF, and $2.8k{\Omega}$ resistor.

• Proceedings of the KIEE Conference
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• 1999.11c
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• pp.742-744
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• 1999

In this paper, a new precharge type PFD for fast locking time of PLL is suggested. It is realized by inserting NMOS transistor and inverter into the precharge part of PFD for isolating the reset of the Up signal from the feedback signal. The new precharge type PFD generates the Up signal while the feedback signal is fixed at a high level. Therefore the new PFD output is increased than the conventional precharge type PFD output. As a result of the increased PFD output, fast locking of PLLs is achieved. Additionally, with control the falling time of the inverter, the dead-zone is reduced and the jitter characteristics are improved. The whole characteristics of PFD and PLL are simulated by using HSPICE. Simulation results show that the dead-zone is 20ps and the locking time of PLL using the new PFD is 38ns at the 350MHz frequency of referecne signal. This value is quite small compared with conventional PFD.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2003.07b
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• pp.1188-1191
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• 2003

In this paper, we focus our attention on the improvement of locking time and jitter parameter and propose the new structure of PLL which combined with the FVC, FOVI Matcher(FVC-Output and VCO-input Matching Circuit), Control Circuit and the conventional charge pump PLL. Using fast operation characteristics of the FVC, the circuit matching FVC-Output and VCO-input (FOVI Matcher) made to synchronize very fast. Fast locking time is usually required for application where the PLL has to settle rapidly if they switch from an idle mode to a normal mode and to track high-frequency data bit rate in data recovery systems. After a fast acqusition is achieved by the using the FVC, the conventional PLL operates for removing the phase error between the reference signal and the feedback signal. Therefore this structure can improve the trade-off between acquisition behavior and locked behavior.