• The Journal of Korean Institute of Communications and Information Sciences
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• v.32 no.1A
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• pp.134-141
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• 2007

This paper presents a frequency synthesizer(FS) for 5.2GHz/2.4GHz dual band wireless applications which is designed in a standard $0.18{\mu}m$ CMOS1P6M process. The 2.4GHz frequency is obtained from the 5.2GHz output frequency of Voltage Controlled Oscillator (VCO) by using the Switched Capacitor (SC) and the divider-by-2. Power dissipations of the proposed FS and VCO are 25mW and 3.6mW, respectively. The tuning range of VCO is 700MHz and the locking time is $4{\mu}s$. The simulated phase noise of PLL is -101.36dBc/Hz at 200kHz offset frequency from 5.0GHz with SCA circuit on.

• Korean Journal of Audiology
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• v.24 no.2
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• pp.71-78
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• 2020

Background and Objectives: Currently limited information is available on speech stimuli processing at the subcortical level in the recipients of cochlear implant (CI). Speech processing in the brainstem level is measured using speech-auditory brainstem response (S-ABR). The purpose of the present study was to measure the S-ABR components in the sound-field presentation in CI recipients, and compare with normal hearing (NH) children. Subjects and Methods: In this descriptive-analytical study, participants were divided in two groups: patients with CIs; and NH group. The CI group consisted of 20 prelingual hearing impairment children (mean age=8.90±0.79 years), with ipsilateral CIs (right side). The control group consisted of 20 healthy NH children, with comparable age and sex distribution. The S-ABR was evoked by the 40-ms synthesized /da/ syllable stimulus that was indicated in the sound-field presentation. Results: Sound-field S-ABR measured in the CI recipients indicated statistically significant delayed latencies, than in the NH group. In addition, these results demonstrated that the frequency following response peak amplitude was significantly higher in CI recipients, than in the NH counterparts (p<0.05). Finally, the neural phase locking were significantly lower in CI recipients (p<0.05). Conclusions: The findings of sound-field S-ABR demonstrated that CI recipients have neural encoding deficits in temporal and spectral domains at the brainstem level; therefore, the sound-field S-ABR can be considered an efficient clinical procedure to assess the speech process in CI recipients.

• Journal of Audiology & Otology
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• v.24 no.2
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• pp.71-78
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• 2020

Background and Objectives: Currently limited information is available on speech stimuli processing at the subcortical level in the recipients of cochlear implant (CI). Speech processing in the brainstem level is measured using speech-auditory brainstem response (S-ABR). The purpose of the present study was to measure the S-ABR components in the sound-field presentation in CI recipients, and compare with normal hearing (NH) children. Subjects and Methods: In this descriptive-analytical study, participants were divided in two groups: patients with CIs; and NH group. The CI group consisted of 20 prelingual hearing impairment children (mean age=8.90±0.79 years), with ipsilateral CIs (right side). The control group consisted of 20 healthy NH children, with comparable age and sex distribution. The S-ABR was evoked by the 40-ms synthesized /da/ syllable stimulus that was indicated in the sound-field presentation. Results: Sound-field S-ABR measured in the CI recipients indicated statistically significant delayed latencies, than in the NH group. In addition, these results demonstrated that the frequency following response peak amplitude was significantly higher in CI recipients, than in the NH counterparts (p<0.05). Finally, the neural phase locking were significantly lower in CI recipients (p<0.05). Conclusions: The findings of sound-field S-ABR demonstrated that CI recipients have neural encoding deficits in temporal and spectral domains at the brainstem level; therefore, the sound-field S-ABR can be considered an efficient clinical procedure to assess the speech process in CI recipients.

• Current Optics and Photonics
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• v.7 no.6
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• pp.738-744
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• 2023

Graphene-based saturable absorbers (SAs) are widely used as laser mode-lockers at various laser oscillators. In particular, transmission-type graphene-SAs with ultrabroad spectral coverage are typically manufactured on transparent substrates with low nonlinearity to minimize the effects on the oscillators. Here, we developed two types of transmitting graphene SAs based on CaF₂ and ZnSe. Using the graphene-SA based on CaF₂, a passively mode-locked mid-infrared Cr:ZnS laser delivers relatively long 540 fs pulses with a maximum output power of up to 760 mW. In the negative net cavity dispersion regime, the pulse width was not reduced further by inhomogeneous group delay dispersion (GDD) compensation. In the same laser cavity, we replaced only the graphene-SA based on CaF₂ with the SA based on ZnSe. Due to the additional self-phase modulation effect induced by the ZnSe substrate with high nonlinearity, the stably mode-locked Cr:ZnS laser produced Fourier transform-limited ~130 fs near 2,340 nm. In the stable single-pulse operation regime, average output powers up to 635 mW at 234 MHz repetition rates were achieved. To our knowledge, this is the first attempt to achieve shorter pulse widths from a polycrystalline Cr:ZnS laser by utilizing the graphene deposited on the substrate with high nonlinearity.

• Journal of the Institute of Electronics Engineers of Korea SC
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• v.44 no.1
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• pp.74-84
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• 2007

This paper presents a new dual-loop Delay Locked Loop(DLL) to expand the delay lock range of a conventional DLL. The proposed dual-loop DLL contains a Coarse_loop and a Fine_loop, and its operation utilizes one of the loops selected by comparing the initial time-difference among the reference clock and 2 internal clocks. The 2 internal clock signals are taken, respectively, at the midpoint and endpoint of a VCDL and thus are $180^{\circ}$ separated in phase. When the proposed DLL is out of the conventional lock range, the Coarse_loop is selected to push the DLL in the conventional lock range and then the Fine_loop is used to complete the locking process. Therefore, the proposed DLL is always stably locked in unless it is harmonically false-locked. Since the VCDL employed in the proposed DLL needs two control voltages to adjust the delay time, it uses TG-based inverters, instead of conventional, multi-stacked, current-starved inverters, to compose the delay line. The new VCDL provides a wider delay range than a conventional VCDL In overall, the proposed DLL demonstrates a more than 2 times wider lock range than a conventional DLL. The proposed DLL circuits have been designed, simulated and proved using 0.18um, 1.8V TSMC CMOS library and its operation frequency range is 100MHz${\sim}$1GHz. Finally, the maximum phase error of the DLL locked in at 1GHz is less than 11.2ps showing a high resolution and the simulated power consumption is 11.5mW.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.24 no.7B
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• pp.1313-1321
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• 1999

The two-phase locking protocol(2PL) is the most widely-used concurrency control mechanism for guaranteeing logical consistency of data in a database environment where a number of transactions perform concurrently. The problem inherent in the 2PL protocol is a deadlock, where a set of transactions holding some locks indefinitely wait an additional lock that is already held by other transactions in the set. The deadlock detector is a DBMS sub-component that examines periodically whether a system is in a deadlock state based on lock waiting information of transactions. The deadlock detector and transactions execute concurrently in a DBMS and read and/or write the lock waiting information simultaneously. Since the lock waiting information is a shared one, we need an efficient method guaranteeing its physical consistency by using mutual exclusion. The efficiency of the mutual exclusion method is crucial especially in a main memory DBMS with high performance since it seriously affects the performance of an entire system. In this paper, we propose a new method that effectively guarantees physical consistency of lock waiting information. Two primary goals of our method are to minimize the processing overhead and to maximize system concurrency.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.45 no.12
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• pp.65-72
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• 2008

This paper proposes a new dual-loop digital PLL(DPLL) using seamless frequency tracking methods. The dual-loop construction, which is composed of the coarse and fine loop for fast locking time and a switching noise suppression, is used successive approximation register technique and TDC. The proposed DPLL in order to compensate the quality of jitter which follows long-term of input frequency is newly added cord conversion frequency tracking method. Also, this DPLL has VCO circuitry consisting of digitally controlled V-I converter and current-control oscillator (CCO) for robust jitter characteristics and wide lock range. The chip is fabricated with Dongbu HiTek $0.18-{\mu}m$ CMOS technology. Its operation range has the wide operation range of 0.4-2GHz and the area of $0.18mm^2$. It shows the peak-to-peak period jitter of 2 psec under no power noise and the power dissipation of 18mW at 2GHz through HSPICE simulation.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.16 no.8
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• pp.5534-5540
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• 2015

This In the railway signaling system, applications of axle counter in addition to track circuit goes on increasing for detecting train position. Consequently, this paper compares sensor methods of axle counter with between geo-magnetism method and proximity sensor method. And it presents differences and results, to improve reliabilities of train detection and axle counting. Also, this article presents an applied result which is based on field experience, with regard to installation, considering attachment condition of sensor part for accurate axle counting. This study acquires expandability that is able to perform not only axle counting function but also various other functions (direction detection of train, speed detection of train, and so on). It was a result of a change of design in order to judge phase difference of sensors, to improve reliability of axle counting. Furthermore, it does not subordinate to characteristics (type, weight of train). And it is confirmed that the omission of axle counting was not occurred in 350km/h. This was the result of Lab test after the construction of transfer equipment of trial axle and Test Bed for axle counting. Both of them are self-productions. Through this, it prepares foundation which is able to apply not only to train detection but also to speed of passing trains, formation number of trains, detector locking condition - when the train passes the section of switch point, and level crossing devices. Furthermore, it would be judged to contribute safety train operation if proximity sensor method applies to the whole railway signaling system from now on.

• Journal of KIISE:Databases
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• v.28 no.3
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• pp.468-483
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• 2001

In order to enhance the performance, cursor stability, which is a variant of isolation lvel 2 in relational DBMSs, has been widely used in place of isolation level 3, which uses strict two phase locking. However, cursor stability is much less usable in object-relational DBMSs (ORDBMSs) because navigational applications in ORDBMSs can suffer from critical inconsistency problems such as dangling pointers, lost updates, and reading inconsistent complex objects. In this paper, we propose a new isolation level, navigation stability, that prevents the inconsistency problems of cursor stability for navigational applications, while avoiding significant degradation of the concurrency of level 3. First, we analyze the inconsistency problems of cursor stability for navigational applications. Second, we define navigation stability as an extension of cursor stability and show that it solves those inconsistency problems of cursor stability in ORDBMSs. For workloads consisting of transactions of long duration, compared with level 3, the throughput of navigation stability is enhanced by up to 200%; the average response time reduced by as much as 55%; and the abort ratio reduced by as much as 77%. From these results, we conclude that navigation stability is a useful isolation level in ORDBMSs that can be used in place of isolation level 3 to improve the performance and concurrency without significantly sacrificing consistency.