• Journal of Advanced Marine Engineering and Technology
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• 제28권2호
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• pp.347-353
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• 2004

Neural oscillator can be applied to oscillator systems such as analysis of image information, voice recognition and etc, Conventional learning algorithms(Neural Network or EBPA(Error Back Propagation Algorithm)) are not proper for oscillatory systems with the complicate input patterns because of its too much complex structure. However, these problems can be easily solved by using a synchrony characteristic of neural oscillator with PLL(phase locked loop) function and a simple Hebbian learning rule, Therefore, in this paper, it will introduce an technique for Recognition of the Korean Character using Phase Synchronization Neural Oscillator and will show the result of simulation.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2013년도 전력전자학술대회 논문집
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• pp.47-48
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• 2013

In order to evaluate the response of the grid-connected systems, Phase lock technology is widely used in power electronic devices to obtain the phase angle, amplitude, and frequency of the grid voltage because phase locked loop (PLL) algorithms are very important for grid synchronization and monitoring in the grid connected power electronic devices. This paper presents a performance evaluation in tracking grid angular frequency through single phase synchronization techniques which are an enhanced PLL (EPLL), second-order generalized integrator-PLL (SOGI-PLL), and second-order generalized integrator-frequency locked loop (SOGI-FLL). These techniques are properly analyzed through several steps to get the best technique which can track the frequency accurately and smoothly.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.143-145
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• 2005

A typical method to control the single-phase power converter system is to utilize the zero-crossing PLL. However, this method is vulnerable to the voltage disturbance and affects the performance of controller. This paper proposes a new single-phase PLL system that is composed of the adaptive linear combiner and the PI control. The operational principle was analyzed through theoretical approach and the performance was verified through simulations with MATLAB. The proposed PLL system shows rapidness and robustness in control under the voltage disturbances such as the sag, harmonics, and phase jump.

• 반도체디스플레이기술학회지
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• 제14권4호
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• pp.72-77
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• 2015

Three-level diode clamped multilevel inverter, generally known as neutral point clamped (NPC) inverter, has an inherent problem causing neutral point (NP) potential variation. Until now, the NP potential problem of variation has been investigated and lots of solutions have also been proposed. This paper presents a neutral point voltage control technology using the anti-windup PI controller and offset technology of PWM (Pulse Width Modulation) to control the variation of NPC 3-phase three-level inverter neutral point voltage. And the proposed algorithm is tested and verified using a PLL (Phase Locked Loop) in order to synchronize the phase voltage from the line voltage of grid. It significantly improves the voltage balancing under a solar fluctuation conditions of the inverter. Experimental results show the good performance and effectiveness of the proposed method.

• 한국지능시스템학회논문지
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• 제14권1호
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• pp.93-99
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• 2004

Neural oscillator can be applied to oscillatory systems such as analyses of image information, voice recognition and etc. Conventional EBPA (Error back Propagation Algorithm) is not proper for oscillatory systems with the complicate input`s patterns because of its tedious training procedures and sluggish convergence problems. However, these problems can be easily solved by using a synchrony characteristic of neural oscillator with PLL(Phase Locked Loop) function and by using a simple Hebbian learning rule. Therefore, in this paper, a technique for Recognition of the Korean Alphabet using Phase Synchronized Neural Oscillator was introduced.

• Journal of Power Electronics
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• 제14권3호
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• pp.608-620
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• 2014

In this paper, an adaptive neural phase-locked loop (AN-PLL) based on adaptive linear neuron is proposed for grid-connected doubly fed induction generator (DFIG) synchronization. The proposed AN-PLL architecture comprises three stages, namely, the frequency of polluted and distorted grid voltages is tracked online; the grid voltages are filtered, and the voltage vector amplitude is detected; the phase angle is estimated. First, the AN-PLL architecture is implemented and applied to a real three-phase power supply. Thereafter, the performances and robustness of the new AN-PLL under voltage sag and two-phase faults are compared with those of conventional PLL. Finally, an application of the suggested AN-PLL in the grid-connected DFIG-decoupled control strategy is conducted. Experimental results prove the good performances of the new AN-PLL in grid-connected DFIG synchronization.

• JSTS:Journal of Semiconductor Technology and Science
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• 제16권6호
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• pp.860-866
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• 2016

An injection-locked ring phase-locked loop (ILRPLL) using a charge-stored complementary switch (CSCS) injection technique is described in this paper. The ILRPLL exhibits a wider lock range compared to other conventional ILRPLLs, owing to the improvement of the injection effect by the proposed CSCS. A frequency calibration loop and a device mismatch calibration loop force the frequency error to be zero to minimize jitter and reference spur. The prototype chip fabricated in 65-nm CMOS technology achieves a $285-fs_{rms}$ integrated jitter at GHz from the reference clock of 52 MHz while consuming 7.16 mW. The figure-of-merit of the ILRPLL is -242.4 dB.

• Journal of Power Electronics
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• 제17권1호
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• pp.262-271
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• 2017

This paper studies the performances of five typical Phase-locked Loops (PLLs) for distorted and unbalanced grid, which are the Decoupled Double Synchronous Reference Frame PLL (DDSRF-PLL), Double Second-Order Generalized Integrator PLL (DSOGI-PLL), Double Second-Order Generalized Integrator Frequency-Lock Loop (DSOGI-FLL), Double Inverse Park Transformation PLL (DIPT-PLL) and Complex Coefficient Filter based PLL (CCF-PLL). Firstly, the principles of each method are meticulously analyzed and their unified small-signal models are proposed to reveal their interior relations and design control parameters. Then the performances are compared by simulations and experiments to investigate their dynamic and steady-state performances under the conditions of a grid voltage with a negative sequence component, a voltage drop and a frequency step. Finally, the merits and drawbacks of each PLL are given. The compared results provide a guide for the application of current control, low voltage ride through (LVRT), and unintentional islanding detection.

• 전력전자학회논문지
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• 제23권4호
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• pp.231-239
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• 2018

The phase-locked loop (PLL) is widely used in grid-tie inverter applications to achieve a synchronization between the inverter and the grid. However, its performance deteriorates when the grid voltage is not purely sinusoidal due to the harmonics and the frequency deviation. Therefore, a high-performance PLL must be designed for single-phase inverter applications to guarantee the quality of the inverter output. This paper proposes a simple method that can improve the performance of the PLL for the single-phase inverter under a non-sinusoidal grid voltage condition. The proposed PLL can accurately estimate the fundamental frequency and theta component of the grid voltage even in the presence of harmonic components. In addition, its transient response is fast enough to track a grid voltage within two cycles of the fundamental frequency. The effectiveness of the proposed PLL is confirmed through the PSIM simulation and experiments.

• 한국전자파학회논문지
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• 제23권11호
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• pp.1280-1287
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• 2012

3.2~6.5 GHz 광대역 특성을 갖는 YTO(YIG Tuned Oscillator) 모듈을 설계 및 제작하였다. 위상 잡음 특성을 개선하기 위해 샘플링 믹서를 이용한 offset PLL(Phase Locked Loop) 구조로 설계하였다. 이 방식은 샘플링 믹서, 위상 비교기, 루프 필터, 전류 드라이버 회로, YTO로 구성된다. 측정 결과, 4.5 GHz에서 위상 잡음은 수식으로 도출한 값과 유사한 10 kHz offset 주파수에서 -100 dBc/Hz를 얻었다. 제작된 YTO 모듈의 위상 잡음은 동작 주파수 대역에서 기존 PLL 구조에 비해 10 dB 이상 우수함을 확인하였다.