• Proceedings of the KIEE Conference
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• 2001.11c
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• pp.334-337
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• 2001

In this paper we implemented DDFS and gam-phase dectector which use output of DDFS or any sinusoidal signal input to broaden the usability of DDFS. DDFS is composed of a 32 bits phase accumulator, phase increment registers, ROM and several registers for controlling the operations. It generates the digital data for sine wave up to the half of the clock frequency. To reduce the ROM size and increase the speed, we adopt the algorithms based on Taylor's series expansion method. Data at sparse phase intervals are stored in ROM and sine data between intervals are calculated in hardware. Function of Gain-Phase Extraction consists of sine lookup of DDFS and the optimized multipliers.

• Proceedings of the KIEE Conference
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• 1988.07a
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• pp.705-708
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• 1988

Ultrasound Doppler Diagnostic System utilizes the Doppler effect for measurement of blood velocity. The sign of the Doppler frequency shift represents blood flow direction. Pulsed Doppler System uses Phase detector and zerocrossing method to produce simultaneous independent audio and velocity signals for forward and reverse blood flow direction in the time domain, had been fabricated. But time-domain analyzing such as audio evaluation and zerocrossing detection for instantaneous and mean frequency measurement doesn't, provide both an accurate and quantitative result. Therefore, it is necessary to adopt frequency domain technique to improve system performance. In this paper, we describe a unit which is composed of Pulsed Doppler System and real-time spectrum analyzer (installed TMS 32010 DSP Chip). This unit shows time-dependent spectrum variation and mean velocity of blood Signal.

• Proceedings of the KIPE Conference
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• 2008.06a
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• pp.103-105
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• 2008

In grid-interconnection system, a fast, robust and precise phase angle detector is most important to grid synchronization and the active power control. The phase angle can be easily estimated by synchronous dq PLL system. On the other hand under unbalanced voltage condition, synchronous dq PLL system has problem that harmonics occur to phase angle or magnitude of grid voltage because of the effect of the negative sequence components. So, To eliminate the negative sequence components, the PLL method using APF (All Pass Filter) in a stationery reference frame to extract positive sequence components under unbalanced voltage condition is researched. In this paper, we propose a new PLL method with decoupling network using APF in a synchronous reference frame to extract the positive sequence components of the grid voltage under unbalanced grid. The cut-off frequency of APF in a synchronous reference frame can be set to twice of the fundamental frequency comparing with that of APF in a stationery reference frame which is the fundamental frequency. The proposed PLL strategy can detect the phase angle quickly and accurately under unbalanced gird voltages. Simulation and experimental results are presented to verify the proposed strategy under different kind of voltage dips.

• Journal of Biomedical Engineering Research
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• v.28 no.2
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• pp.229-234
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• 2007

Diffuse optical tomography (DOT) is a relatively new medical imaging modality which uses near infrared light to image large-sized tissues noninvasively. We constructed a frequency-domain DOT system to measure the optical properties of optical phantoms and human tissues. The FD-DOT uses the intensity-modulated infrared light source that illuminates the biological tissues. The phase shift and modulation changes at each detector site are separately processed to measure the optical properties. The absorption and scattering coefficients are separately estimated using inverse algorithms.

• Proceedings of the KIEE Conference
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• 1996.07b
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• pp.1301-1303
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• 1996

A new automatic frequency control(AFC) tracking algorithm, which we call a rotational decision directed AFC(RDDAFC) is proposed for QPSK demodulation at the digital direct broadcasting satellite(DBS). In order to prevent the presence of the residual phase difference between symbols received at k and k-l by the CPAFC[1] as well as the AFC based on $tan^{-1}$ circuit[2], the RDDAFC rotates the decision boundary for the kth received symbol by the frequency detector output of the (k-1)th received symbol before passing through the cross product discriminator. Test results show that the total pull-in time of the RDDAFC and PLL was 0.13msec under a carrier frequency offset of 2.4MHz when S/N equals 2dB.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.967-973
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• 2009

In this paper, X-band satellite communication oscillator of double phase locked is implemented by constructing a couple of phased-locked loop, and then we have analyzed the phase noise of designed PLL-DRO. The designed phase-locked oscillator is consist of series feedback DRO, frequency divider, phase detector, loop filter and programmable PLL-IC. By dividing oscillation frequency of 12.6 GHz into two frequencies, it exhibits output power of 15.32 dBm at 6.3 GHz. Phase noises of implemented oscillator are -81 dBc/Hz@100Hz, -100.86 dBc/Hz@1 kHz, -111.12 dBc/Hz@10 kHz, -116 dBc/Hz@100 kHz and -140.49 dBc/Hz@1 MHz respectively. These indicate excellent stable operation of oscillator and very good phase noise characteristics.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.4A
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• pp.247-255
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• 2003

In this paper, an $tan^{-1}$ circuit for the frequency synchronization of OFDM based IEEE 802.11a is presented. The proposed circuit consists of a divider, an $tan^{-1}$ ROM and a phase detector, which can detect frequency offset within 0.0491 rad. The circuit implemented with FPGA shows a pull-in range of under ${\pm}625KHz$ at 5dB AWGN. It may be useful for IEEE 802.11a WLAN standard.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.26 no.12C
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• pp.255-260
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• 2001

This paper describes the design of the Register Controlled DLL(Delay-Locked Loop) that achieves fast locking and low Power consumption using a new locking algorithm. A fashion for a fast locking speed is that controls the two controller in sequence. The up/down signal due to clock skew between a internal and a external clock in phase detector, first adjusts a large phase difference in coarse controller and then adjusts a small phase difference in fine controller. A way for a low power consumption is that only operates one controller at once. Moreover the proposed DLL shows better jitter performance Because using the lock indicator circuit. The proposed DLL circuit is operated from 50MHz to 200MHz by SPICE simulation. The estimated power dissipation is 15mA at 200MHz in 3.3V operation. The locking time is within 7 cycle at all of operating frequency.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.19 no.10
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• pp.1973-1981
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• 1994

A PLDRO(Phase Locked Dielectric Resonator Oscillator) in Ku-band(10.95-11.70GHz) is designed with the concept of the feedback property of PLL(Phase Locked Loop). A series feedback type DRO is developed, and VCDRO(Voltage Controlled Dielectric Resonator Oscillator) using a varactor diode as a voltage-variable capacitor is implemented to tune oscillating frequency electrically. Then, PLDRO is designed by using a SPD(Sampling Phase Detector). This PLDRO is phase-locked voltage controlled DRO to reference source(VHF band) by SPD at 10.00 GHz for European FSS(Fixed Satellite Service). The PLDRO generates output power greater than 10dBm at 10.00 GHz and has phase noise of -80 dBc/Hz at 10 KHz offset from carrier. This PLDRO achieves much better frequency stability than conventional VCDRO.

• Journal of Sensor Science and Technology
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• v.8 no.6
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• pp.427-433
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• 1999

In this paper, we have presented an one-axis fluxgate magnetic sensor with ferrite core, excitation, and pick-up coil. This magnetometer is consist of a sensing element, driving circuits for excitation coil and signal processing for detecting second harmonic frequency component which is proportional to the DC magnetic to be measured. The sensor core is excited by a square waveform of voltage through 82 turns of the excitation coil. The second harmonic output of pick-up coil(150 turns) is measured by a FFT spectrum analyzer. This result is compared to output of PSD(phase sensitive detector) unit for detecting a second harmonic component. The measured sensitivity is about 50 V/T at driving frequency of 2 kHz. The nonlinearity of fluxgate magnetic sensor is calculated about 2.0%.