• Proceedings of the Korea Database Society Conference
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• 1998.09a
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• pp.347-364
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• 1998

Oracle's KM Technology ㆍCore Technologies - Oracle Application Server 4.0 JCORBA Cartridge, JTS - Oracle 8.1 JavaVM, Java Stored Procedure, CORBA/ORB, IIOP - ConText Carridge 8.1 - Enterprise Scalability and Performance - Open SQL Query Layer - Fully-Extensible Object Model for custom solutions ㆍNext Plan - Oracle Application Server 4.1 EJB Cartridge(omitted)

• Journal of the Korea Institute of Information and Communication Engineering
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• v.14 no.1
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• pp.138-144
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• 2010

Tachyon primary system which introduces recently is a high performance supercomputer that composed with AMD Barcelona nodes. In this paper, we will verify the performance and parallel scalability of TachyonIn by using multi-zone NAS Parallel Benchmark(NPB) which is one of a program with hybrid parallel method. To test performance of hybrid parallel execution, B and C classes of BT-MZ in NPB version 3.3 were used. And the parallel scalability test has finished with Tachyon's 1024 processes. It is the first time in Korea to get a result of hybrid parallel computing calculation using more than 1024 processes. Hybrid parallel method in high performance computing system with multi-core technology like Tachyon describes that it can be very efficient and useful parallel performance benchmarks.

• Proceedings of the Korean Operations and Management Science Society Conference
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• 2005.05a
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• pp.621-628
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• 2005

Scalability of clustering algorithms is critical issues facing the data mining community. This is particularly true for computationally intense tasks such as data clustering. Random sampling of instances is one possible means of achieving scalability but a pervasive problem with this approach is how to deal with the noise that this introduces in the evaluation of the learning algorithm. This paper develops a new optimization based clustering approach using an algorithms specifically designed for noisy performance. Numerical results illustrate that with this algorithm substantial benefits can be achieved in terms of computational time without sacrificing solution quality.

• Journal of Communications and Networks
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• v.8 no.1
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• pp.123-131
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• 2006

Several distributed architectures, incorporating mobile agent technology, have been recently proposed to answer the scalability limitations of their centralized counterparts. However, these architectures fail to address scalability problems, when distributed tasks requiring the employment of itinerant agents is considered. This is because they lack mechanisms that guarantee optimization of agents' itineraries so as to minimize the total migration cost in terms of the round-trip latency and the incurred traffic. This is of particular importance when MAs itineraries span multiple subnets. The work presented herein aspires to address these issues. To that end, we have designed and implemented an algorithm that adapts methods usually applied for addressing network design problems in the specific area of mobile agent itinerary planning. The algorithm not only suggests the optimal number of mobile agents that minimize the overall cost but also constructs optimal itineraries for each of them. The algorithm implementation has been integrated into our mobile agent framework research prototype and tested in real network environments, demonstrating significant cost savings.

• Journal of Communications and Networks
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• v.8 no.4
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• pp.378-390
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• 2006

Many distributed applications build overlays on top of the Internet. Several unsolved issues at the network layer can explain this trend to implement network services such as multicast, mobility, and security at the application layer. On one hand, overlays creating basic topologies are usually limited in flexibility and scalability. On the other hand, overlays creating complex topologies require some form of application level addressing, routing, and naming mechanisms. Our aim is to design an efficient and robust addressing, routing, and naming infrastructure for these complex overlays. Our only assumption is that they are deployed over the Internet topology. Applications that use our middleware will be relieved from managing their own overlay topologies. Our infrastructure is based on the separation of the naming and the addressing planes and provides a convergence plane for the current heterogeneous Internet environment. To implement this property, we have designed a scalable distributed k-resilient name to address binding system. This paper describes the design of our overlay infrastructure and presents performance results concerning its routing scalability, its path inflation efficiency and its resilience to network dynamics.

• Electronics and Telecommunications Trends
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• v.13 no.5 s.53
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• pp.11-22
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• 1998

Recently, scalable multiprocessor systems are actively developed for general-purpose computing, which are based on distributed shared memory (DSM) architecture to boost up both programmability and scalability. In this paper, we survey and analyze cache coherence protocols in non-uniform memory access (NUMA) multiprocessor systems. In particular, it has been easily inferred that specialized hardware suitable for NUMA multiprocessor systems with commodity symmetric multiprocessors (SMPs) is highly required. The cache coherence protocol combined with specialized hardware can significantly improve the performance and scalability of NUMA multiprocessor systems, providing better programmability.

• IEIE Transactions on Smart Processing and Computing
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• v.5 no.5
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• pp.337-345
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• 2016

Recently, as the number of cores in computer systems has increased, the need for larger memory capacity has also increased. Unfortunately, dynamic random access memory (DRAM), popularly used as main memory for decades, now faces a scalability limitation. Phase change memory (PCM) is considered one of the strong alternatives to DRAM due to its advantages, such as high scalability, non-volatility, low idle power, and so on. However, since PCM suffers from short write endurance, direct use of PCM in main memory incurs a significant problem due to its short lifetime. To solve the lifetime limitation, many studies have focused on reducing the number of bit flips per write request. In this paper, we describe the PCM operating principles in detail and explore various bit flip reduction schemes. Also, we compare their performance in terms of bit reduction rate and lifetime improvement.

• Proceedings of the Korea Information Processing Society Conference
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• 2002.04a
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• pp.381-384
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• 2002

This paper describes the motivation, design and performance of bi-active Load balancer in Linux Virtual Server. The goal of bi-active Load balancer is to provide a framework to build highly scalable, fault-tolerant services using a large cluster of commodity servers. The TCP/IP stack of Linux Kernel is extended to support three IP load balancing techniques, which can make parallel services of different kinds of server clusters to appear as a service on a single IP address. Scalability is achieved by transparently adding or removing a node in the cluster. and high availability is provided by detecting node or daemon failures and reconfiguring the system appropriately. Extensive simulation reveals that the proposed approach improves the reply rate about 20% compared to earlier design.

• Journal of the Semiconductor & Display Technology
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• v.8 no.1
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• pp.19-25
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• 2009

Abstract JPEG2000 achieve quality scalability through the rate control method used in the encoding process, which embeds quality layers to the code-stream. This architecture might raise two drawbacks. First, when the coding process finishes, the number and bit-rates of quality layers are fixed, causing a lack of quality scalability to code-stream encoded with a single or few quality layers. Second, in Post compression rate distortion (PCRD) the bit streams after the truncation points discarded. Therefore, computational power for the discarded bit streams is wasted. For solving of problem, through bit rate control, there are many researches. Each proposed algorithms have specially target feature that is improved performance like reducing computational power. Research results have strength and weakness. For the mean time, research contents are reviewed and compared, so we proposed research direction in the future.

• Proceedings of the KIEE Conference
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• 2007.07a
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• pp.1335-1336
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• 2007

Among the emerging non-volatile memory technologies, phase change memories are the most attractive in terms of both performance and scalability perspectives. Phase-change random access memory(PRAM), compare with flash memory technologies, has advantages of high density, low cost, low consumption energy and fast response speed. However, PRAM device has disadvantages of set operation speed and reset operation power consumption. In this paper, we investigated scalability of $Ge_{1}Se_{1}Te_{2}$ chalcogenide material to improve its properties. As a result, reduction of phase change region have improved electrical properties of PRAM device.