• 대한전자공학회논문지SD
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• 제39권12호
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• pp.1001-1007
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• 2002

된 논문에서는 펜타센을 활성층으로 사용하는 유기박막트랜지스터(OTFT)의 펜타센의 두께, 그리고 소오스 및 드레인 전극의 위치에 따른 소자의 성능 변화에 대하여 연구하였다. 펜타센 박막의 두께가 증가하면 그레인 상태가 박막상태에서 벌크상태로 변화하면서 결정도가 악화되어 성능이 열화하였고, 소오스와 드레인 전극을 펜타센 위에 제작한 소자의 경우 접촉저항은 감소하였으나 누설전류가 증가하여 전류 점멸비가 감소하였다. 그러므로, 펜타센의 두께는, 300Å∼700Å 내외, 그리고 전극은 펜타센 아래에 위치하는 것이 적합한 것으로 확인되었다.

• 한국전기전자재료학회:학술대회논문집
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• 한국전기전자재료학회 2007년도 하계학술대회 논문집 Vol.8
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• pp.395-395
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• 2007

We report on the fabrication of soluble pentacene-based thin-film transistors (TFTs) that consist of $NiO_x$, poly-vinyl phenol (PVP), and Ni for the source-drain (SID) electrodes, gate dielectric, and gate electrode, respectively. The $NiO_x$ SID electrodes of which the work function is well matched to that of soluble pentacene are deposited on a soluble pentacenechannel by sputter deposited of NiO powder and show a moderately low but still effective transmittance of ~65% in the visible range along with a good sheet resistance of ${\sim}40{\Omega}/{\square}$. The maximum saturation current of our soluble pentacene-based TFT is about $15{\mu}A$ at a gate bias of -40showing a high field effect mobility of $0.06cm^2/Vs$ in the dark, and the on/off current ratio of our TFT is about $10^4$. It is concluded that jointly adopting $NiO_x$ for the S/D electrodes and PVP for gate dielectric realizes a high-quality soluble pentacene-based TFT.

• 한국재료학회:학술대회논문집
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• 한국재료학회 2003년도 춘계학술발표강연 및 논문개요집
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• pp.40-40
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• 2003

일반적으로 액티브 매트릭스 구동용 스위칭 소자의 경우 Turn-on 시간은 프레임 주파수와 게이트 라인의 수에 반비례하므로 LCD의 화면이 대면적으로 갈수록 스위칭 주파수는 증가하고 이는 채널에서의 열적 효과(thermal effect)를 유도하게 된다. 그러므로 전도성 유기물이 LCD용 유기박막트랜지스터(Thin Film Transistor) 등의 부품으로서의 적절성을 판단하기 위하여는 이에 대한 열적 특성에 대한 검증이 필요하게 된다. 따라서 본 연구에서는 유기 TFT의 열설계에 있어서 필수적인 물질변수로 인식되는 열적 특성들을 측정 계산하였으며 이를 소자의 열적 모델링에 적용하였다. 실험물질로는 pentacene을 사용하였으며 열확산도는 레이저 플레쉬법을 이용하여 측정하였다. 별도로 측정된 비열ㆍ밀도 등의 물성특성을 이용하여 상온에서 200 C의 온도범위에서 pentacene의 열전도도를 계산하여 그 결과를 열적으로 해석하였다. 계산결과, pentacene의 열전도도는 상온에서 약 0.0024 W/cm K의 값을 나타내었고, 70 C 까지 증가하여 약 0.0035 W/cm K의 정점을 보인 후에 200 C 에서 약 0.0022 W/cm K의 낮은 값을 나타낼 때까지 계속 감소하였다 아울러 본 연구에서는 실제 소자응용 시 박막으로서의 pentacene의 응용을 고려하여 실제 박막형태에 대한 열전도를 측정하였으며 이를 레이저 플레쉬법으로 측정한 값과 비교ㆍ분석하였다.

• Journal of Electrical Engineering and Technology
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• 제4권1호
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• pp.118-122
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• 2009

Organic thin film transistors with a pentacene active layer and various polymer gate insulators were fabricated and their performances were investigated. Characteristics of pentacene thin film transistors on different polymer substrates were investigated using an atomic force microscope (AFM) and x-ray diffraction (XRD). The pentacene thin films were deposited by thermal evaporation on the gate insulators of various polymers. Hexamethyldisilazane (HMDS), polyvinyl acetate (PVA) and polymethyl methacrylate (PMMA) were fabricated as the gate insulator where a pentacene layer was deposited at 40, 55, 70, 85, 100 oC. Pentacene thin films on PMMA showed the largest grain size and least trap concentration. In addition, pentacene TFTs of top-contact geometry are compared with PMMA and $SiO_2$ as gate insulators, respectively. We also fabricated pentacene TFT with Poly (3, 4-ethylenedioxythiophene)-Polysturene Sulfonate (PEDOT:PSS) electrode by inkjet printing method. The physical and electrical characteristics of each gate insulator were tested and analyzed by AFM and I-V measurement. It was found that the performance of TFT was mainly determined by morphology of pentacene rather than the physical or chemical structure of the polymer gate insulator

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.163-166
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• 2002

We studied the growth of large-grain pentacene film by organic vapour phase deposition. The optimizations of the growth of pentacene are carried out by varying the gas pressure in the reactor and substrate temperature. We found that the grain size depends strongly on the gas pressure in the reactor. The grain size of $20{\mu}m$ has been obtained at the gas pressure of 200 Torr. The film was found to be strongly (001) oriented and its grain size decreases with decreasing the gas pressure.

• 청정기술
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• 제30권1호
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• pp.13-22
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• 2024

본 연구에서는 6,13-Bis(triisopropylsilylethynyl)pentacene(TP):2-Decyl-7-phenyl[1]benzothieno[3,2-b][1]benzothiophene(BT):Poly styrene (PS) 블랜딩 thin film transistor (TFT)를 제작 광 흡수 센서로의 활용에 대해 탐구한다. BT의 혼합으로 인해 off current 감소와 on/off ratio 향상을 동시에 달성하였다. 특히, TP:BT:PS (1:0.25:1 w/w) 샘플은 우수한 광 흡수 특성을 보여주었고, 이를 통해 높은 성능의 광 흡수 장치 제작이 가능함을 입증했다. 다양한 혼합 비율의 결정 구조와 전기적 특성에 대한 분석을 통해 TP:BT:PS (1:0.25:1 w/w) 샘플이 최적임을 확인하였다. 이 결과는 광 흡수 장치의 발전 뿐만 아니라 혼합 organic semiconductor (OSC)의 광전자 시스템 개발에 긍정적인 기대효과를 미칠 수 있을 것이며, 이를 통해 단일 OSC 사용의 제약을 극복하고, 미세 조정된 광학 응답을 갖춘 고성능 OSC TFT를 제작하여 의료 전자소자, 산업용 전자소자 등에 응용할 수 있을 것으로 기대된다.

• Macromolecular Research
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• 제10권2호
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• pp.75-79
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• 2002

Organic materials have considerable attention as active semiconductors for device applications such as thin-film transistors (TFTs) and diodes. Pentacene is a p-type organic semiconducting material investigated for TFTs. In this paper, we reported the morphological and electrical characteristics of pentacene TFT films. The pentacene transistors showed the mobility of 0.8 $\textrm{cm}^2$/Vs and the grains larger than 1 ${\mu}{\textrm}{m}$. Deep-level transient spectroscopy (DLTS) measurements were carried out on metal/insulator/organic semiconductor structure devices that had a depletion region at the insulator/organic-semiconductor interface. The duration of the capacitance transient in DLTS signals was several ten of seconds in the pentacene, which was longer than that of inorganic semiconductors such as Si. Based on the DLTS characteristics, the energy levels of hole and electron traps for the pentacene films were approximately 0.24, 1.08, and 0.31 eV above Ev, and 0.69 eV below Ec.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2002년도 International Meeting on Information Display
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• pp.754-758
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• 2002

In order to reach the high quality of organic thin films such as high mobility for device applications, it is strongly desirable to study the growth properties of pentacene film as a function of evaporation condition. Here, we report the structure and morphology of thermal evaporated pentacene thin film by AFM, SEM, and XRD as a function of the evaporation rate and substrate temperature. These results play a key role in determining the electric performance of organic thin film transistor devices.

• 한국응용과학기술학회지
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• 제30권2호
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• pp.290-296
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• 2013

We analysed interfacial traps in organic thin-film transistors (TFTs) in which pentacene and 6,13-bis(triisopropylsilylethynyl)-pentacene (TIPS-pentacene) organic semiconductors were deposited by means of vacuum-thermal evaporation and drop-coating methods, respectively. The thermally-deposited pentacene film consists of dentritic grains with the average grain size of around 1 m, while plate-like crystals over a few hundred microns are observed in the solution-processed TIPS-pentacene film. From the transfer characteristics of both TFTs, lower subthreshold slope of 1.02 V/decade was obtained in the TIPS-pentacene TFT, compared to that (2.63 V/decade) of the pentacene transistor. The interfacial trap density values calculated from the subthreshold slope are about $3.4{\times}10^{12}/cm^2$ and $9.4{\times}10^{12}/cm^2$ for the TIPS-pentacene and pentacene TFTs, respectively. Herein, lower subthreshold slope and less interfacial traps in TIPS-pentacene TFTs are attributed to less domain boundaries in the solution-processed TIPS-pentacene film.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2008년도 International Meeting on Information Display
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• pp.620-621
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• 2008

Transparent electronics has been one of the key terminologies forecasting the ubiquitous technology era. Several researchers have thus extensively developed transparent oxide-based thin-film transistors (TFTs) on glass and plastic substrates although in general high voltage operating devices have been mainly studied considering transparent display drivers. However, low voltage operating oxide TFTs with transparent electrodes are very necessary if we are aiming at logic circuit applications, for which transparent complementary or one-type channel inverters are required. The most effective and low power consuming inverter should be a form of complementary p-channel and n-channel transistors but real application of those complementary TFT inverters also requires electrical- and even photo-stabilities. Since p-type oxide TFTs have not been developed yet, we previously adopted organic pentacene TFTs for the p-channel while ZnO TFTs were chosen for n-channel on sputter-deposited $AlO_x$ film. As a result, decent inverting behavior was achieved but some electrical gate instability was unavoidable at the ZnO/$AlO_x$ channel interface. Here, considering such gate instability issues we have designed a unique transparent complementary TFT (CTFTs) inverter structure with top n-ZnO channel and bottom p-pentacene channel based on 12 nm-thin nano-oxide/self assembled monolayer laminated dielectric, which has a large dielectric strength comparable to that of thin film amorphous $Al_2O_3$. Our transparent CTFT inverter well operate under 3 V, demonstrating a maximum voltage gain of ~20, good electrical and even photoelectric stabilities. The device transmittance was over 60 % and this type of transparent inverter has never been reported, to the best of our limited knowledge.