• Proceedings of the KIEE Conference
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• 1998.07g
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• pp.2518-2520
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• 1998

Silicon can be reactive ion etched (RIE) either isotropically or anisotropically. In this paper, a new micromachining technology combining these two etching characteristics is proposed. In the proposed method, the fabrication steps are as follows. First. a polysilicon layer, which is used as the bottom electrode, is deposited on the silicon wafer and patterned. Then the silicon substrate is etched anisotropically to a few micrometer depth that forms a cavity. Then an PECVD oxide layer is deposited to passivate the cavity side walls. The oxide layers at the top and bottom faces are removed while the passivation layers of the side walls are left. Then the substrate is etched again but in an isotropic etch condition to form a round trench with a larger radius than the anisotropic cavity. Then a sacrificial PECVD oxide layer is deposited and patterned. Then a polysilicon structural layer is deposited and patterned. This polysilicon layer forms a pivot structure of a rocker-arm. Finally, oxide sacrificial layers are etched away. This new micromachining technology is quite simpler than conventional method to fabricate joint structures, and the devices that are fabricated using this technology do not require a flexing structure for motion.

• Bulletin of the Korean Chemical Society
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• v.29 no.7
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• pp.1349-1352
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• 2008

We report a novel patterning method for a homo-polymeric poly(3-hexylthiophene) (P3HT) nanofilm particularly capable of strong adhesion to a $SiO_2$ surface. An oxidized silicon wafer substrate was micro-contact printed with n-octadecyltrichlorosilane (OTS) monolayer, and subsequently its negative pattern was selfassembled with three different amino-functionalized alkylsilanes, (3-aminopropyl)trimethoxysilane (APS), N- (2-aminoethyl)-3-aminopropyltrimethoxy silane (EDAS), and (3-trimethoxysilylpropyl) diethylenetriamine (DETAS). Then, P3HT nanofilms were selectively grown on the aminosilane pre-patterned areas via the vapor phase polymerization method. To evaluate the adhesion, patterning, and the film itself, the PEDOT nanofilms and SAMs were investigated with a $Scotch^{(R)}$ tape test, contact angle analyzer, ATR-FT-IR, and optical and atomic force microscopes. The evaluation showed that the newly developed all bottom-up process can offer a simple and inexpensive patterning method for P3HT nanofilms robustly adhered to an oxidized Si wafer surface by the mediation of $FeCl_3$ and amino-functionalized alkylsilane SAMs.

• Journal of the Korean Vacuum Society
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• v.6 no.1
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• pp.9-19
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• 1997

The reaction mechanisms of dry cleaning with UV-excited chlorine radical for Zn, Fe and Ti trace contaminants on the Si wafer have been studied by SEM, AFM and XPS analyses in this work. The patterned Zn, Fe and Ti films were deposited on the Si wafer surface by thermal evaporation and changes in the surface morphology after dry cleaning with $Cl_2$and UV/$Cl_2$at $200^{\circ}C$ were studied by optical microscopy and SEM. In addition, changes in the surface roughness of Si wafer with the cleaning was observed by AFM. The chemical bonding states of the Zn, Fe and Ti deposited silicon surface were observed with in-line XPS analysis. Zn and Fe were easily cleaned in the form of volatile zinc-chloride and iron-chloride as verified by the surface morphology changes. Ti which forms involatile oxides was not easily removed at room temperature but was slightly removed by UV/$Cl_2$at elevated temperature of $200^{\circ}C$. It was also found that the surface roughness of the Si wafer increased after $Cl_2$and UV/$Cl_2$cleaning. Therefore, the metallic contaminants on the Si wafer can be easily removed at lower temperature without surface damage by a continuous process using wet cleaning followed by UV/$Cl_2$dry cleaning.

• 한국신재생에너지학회:학술대회논문집
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• 2010.11a
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• pp.53.2-53.2
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• 2010

In this study, we focused on our specialized electrode process for Si back-contact crystalline solar cell. It is different from other well-known back-contact cell process for thermal aspect and specialized process. In general, aluminum makes ohmic contact to the Si wafer and acts as a back surface reflector. And, silver is used for low series resistance metal grid lines. Aluminum was sputtered onto back side of wafer. Next, silver is directly patterned on the wafer by screen printing. The sputtered aluminum was removed by wet etching process after rear silver electrode was formed. In this process, the silver paste must have good printability, electrical property and adhesion strength, before and after the aluminum etching process. Silver paste also needs low temperature firing characteristics to reduce the thermal budget. So it was seriously collected by the products of several company of regarding low temperature firing (below $250^{\circ}C$) and aluminum etching endurance. First of all, silver pastes for etching selectivity were selected to evaluate as low temperature firing condition, electrical properties and adhesive strength. Using the nano- and micron-sized silver paste, so called hybrid type, made low temperature firing. So we could minimize the thermal budget in metallization process. Also the adhesion property greatly depended on the composition of paste, especially added resin and inorganic additives. In this paper, we will show that the metallization process of back-contact solar cell was realized as optimized nano-paste characteristics.

• Journal of the Optical Society of Korea
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• v.18 no.5
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• pp.569-573
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• 2014

We demonstrate a low-cost, superbly efficient way of etching for the nano-, and micro-sized pyramid patterns on (100)-oriented Si wafer surfaces for use as a patterned master. We show a way of producing functional optical films for the viewing angle direction brightness-enhancement of Lambertian LED (light emitting diode)/OLED (organic light emitting diode) planar lighting applications. An optimally formulated KOH (Potassium hydroxide) wet etching process enabled random-positioned, and random size-distributed (within a certain size range) pyramid patterns to be developed over the entire (100) silicon wafer substrates up to 8" and a simple replication process of master patterns onto the PC (poly-carbonate) and PMMA (poly-methyl methacrylate) films were performed. Haze ratio values were measured for several film samples exhibiting excellent values over 90% suitable for LED/OLED lighting purposes. Brightness was also improved by 13~14% toward the viewing angle direction. Computational simulations using LightTools$^{TM}$ were also carried out and turned out to be in strong agreement with experimental data. Finally, we could check the feasibility of fabricating low-cost, large area, high performance optical films for commercialization.

• Particle and aerosol research
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• v.18 no.4
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• pp.129-136
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• 2022

The line width of circuits in semiconductor devices continues to decrease down to a few nanometers. Since nanoparticles attached to the patterned wafer surface may cause malfunction of the devices, it is crucial to remove the contaminant nanoparticles. Physical cleaning that utilizes momentum of liquid for detaching solid nanoparticles has recently been tested in place of the conventional chemical method. Dropwise impaction has been employed to increase the removal efficiency with expectation of more efficient momentum exchange. To date, most of relevant studies have been focused on drop spreading behavior on a horizontal surface in terms of maximum spreading diameters and average spreading velocity of drop. More important is the local liquid velocity at the position of nanoparticle, very near the surface, rather than the vertical average value. In addition, there are very scarce existing studies dealing with microdroplet impaction that may be desirable for minimizing pattern demage of the wafer. In this study, we investigated the local velocity distribution in spreading liquid film under various impaction conditions through the CFD simulation. Combining the numerical results with the particle removal model, we estimated an effective cleaning diameter (ECD), which is a measure of the particle removal capacity of a single drop, and presented the predicted ECD data as a function of droplet's velocity and diameter particularly when the droplets are microns in diameter.

• Transactions on Electrical and Electronic Materials
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• v.6 no.5
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• pp.225-228
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• 2005

In this work, we studied the optimized copper thickness in Cu ECP (Electrochemical Plating). In order to select an optimized Cu ECP thickness, we examined Cu ECP bulge (bump, hump or over-plating amount), Cu CMP dishing and electrical properties of via hole and line trench over dual damascene patterned wafers split into different ECP Cu thickness. In the aspect of bump and dishing, the bulge increased according as target plating thickness decreased. Dishing of edge was larger than center of wafer. Also in case of electrical property, metal line resistance distribution became broad gradually according as Cu ECP thickness decreased. In conclusion, at least $20\%$ reduced Cu ECP thickness from current baseline; $0.8\;{\mu}m$ and $1.0\;{\mu}m$ are suitable to be adopted as newly optimized Cu ECP thickness for local and intermediate layer.

• 한국정보디스플레이학회:학술대회논문집
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• 2006.08a
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• pp.703-706
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• 2006

Zinc oxide nanocrystals are attractive candidates for a solution-processable semiconductor for high performance thin film field effect transistors. We have studied ZnO thin film transistor fabricated by solution process and have improved $V_{th}$ by controlling the ZnO ink additives. Synthesized ZnO nanoparticles of 30nm were dispersed in solvent to make the ZnO ink. ZnO ink was spin coated on silicon wafer and after heat treatment electrodes were patterned.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2012.10a
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• pp.586-589
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• 2012

In this paper, a tunable capacitor like an interdigital one is presented for low-voltage applications. In order to reduce operation voltage by enhancing fringing electric fields, two finger-patterned electrodes are vertically separated by employing a multi-layer thin film dielectric of a para-/ferro-/para-electrics without spacing between electrodes. The proposed tunable capacitor was fabricated on a quartz wafer and its characteristics are analyzed in terms of effective capacitance and tunability with a function of applied voltages, compared to the conventional interdigital capacitor (IDC). At 8V and 2 GHz, the proposed tunable capacitor shows the tunability of 18 % that is 10.3 % higher than that of the compared one.

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2006.05a
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• pp.533-534
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• 2006

Micro pyramid pattern and its array are designed to enhance the brightness and its uniformity of LGP which is one of key parts in LCD. The designed micro pyramid patterns are fabricated on a Si-wafer first through MEMS process and then a Ni-stamper is electro-plated from the Si pattern master. Adopting the fabricated Ni-stamper, LGPs are injection molded at different mold temperatures and the fidelity of the pattern replication is estimated for each molding conditions and pattern locations. The replicated patterns are found to have some defect such as local short shot or micro weld line which are believed to have negative effect on the performance of the LGP.