• Title/Summary/Keyword: path-switching

Search Result 265, Processing Time 0.023 seconds

Analysis of Emission Characteristics of DC/DC Converter with different Parts Layout (부품배치가 다르게 제작된 DC/DC컨버터의 Emission 특성분석)

  • Park, Jin-Hong
    • Journal of the Korea Academia-Industrial cooperation Society
    • /
    • v.20 no.1
    • /
    • pp.179-183
    • /
    • 2019
  • The system stability must be ensured from the switching noise due to the power conversion efficiency and power conversion system miniaturization. Therefore, countermeasures to reduce switching noise during power conversion are essential. Thus, in the previous paper, we constructed the DC / DC Buck Converter circuit using MPQ4432 driver of MPS, and simulated the switching noise characteristics which occurs when the components are arranged differently in the 4 - layer PCB circuit structure with reference plane. In this paper, two different simulated circuits are fabricated and the characteristics of the conducted emission and the radiated emission are analyzed in the same way as the simulation. As a result, it was confirmed that the Conducted Emission characteristic was reduced by 2 ~ 9dB in the low frequency band and 6 ~ 7dB in the high frequency band depending on the configuration of the current return path. And the radiated emission characteristic is reduced by 9 dB. Conducted emission simulation results show that 6 ~ 7dB in the low frequency range and 2 ~ 9dB in the measurement result are somewhat different. In the high frequency band, it is confirmed that the experimental and simulation results are about 7dB. And Radiated Emission confirmed 12dB decrease in simulation, but confirmed decrease of 9dB in measurement result. It is confirmed that there is a slight difference in the amount of reduction, but the design of the power conversion circuit improves the noise characteristics according to the configuration of the current return path.

Parking Path Planning For Autonomous Vehicle Based on Deep Learning Model (자율주행차량의 주차를 위한 딥러닝 기반 주차경로계획 수립연구)

  • Ji hwan Kim;Joo young Kim
    • The Journal of The Korea Institute of Intelligent Transport Systems
    • /
    • v.23 no.4
    • /
    • pp.110-126
    • /
    • 2024
  • Several studies have focused on developing the safest and most efficient path from the current location to the available parking area for vehicles entering a parking lot. In the present study, the parking lot structure and parking environment such as the lane width, width, and length of the parking space, were vaired by referring to the actual parking lot with vertical and horizontal parking. An automatic parking path planning model was proposed by collecting path data by various setting angles and environments such as a starting point and an arrival point, by putting the collected data into a deep learning model. The existing algorithm(Hybrid A-star, Reeds-Shepp Curve) and the deep learning model generate similar paths without colliding with obstacles. The distance and the consumption time were reduced by 0.59% and 0.61%, respectively, resulting in more efficient paths. The switching point could be decreased from 1.3 to 1.2 to reduce driver fatigue by maximizing straight and backward movement. Finally, the path generation time is reduced by 42.76%, enabling efficient and rapid path generation, which can be used to create a path plan for autonomous parking during autonomous driving in the future, and it is expected to be used to create a path for parking robots that move according to vehicle construction.

Novel Power Bus Design Method for High-Speed Digital Boards (고속 디지털 보드를 위한 새로운 전압 버스 설계 방법)

  • Wee, Jae-Kyung
    • Journal of the Institute of Electronics Engineers of Korea SD
    • /
    • v.43 no.12 s.354
    • /
    • pp.23-32
    • /
    • 2006
  • Fast and accurate power bus design (FAPUD) method for multi-layers high-speed digital boards is devised for the power supply network design tool for accurate and precise high speed board. FAPUD is constructed, based on two main algorithms of the PBEC (Path Based Equivalent Circuit) model and the network synthesis method. The PBEC model exploits simple arithmetic expressions of the lumped 1-D circuit model from the electrical parameters of a 2-D power distribution network. The circuit level design based on PBEC is carried with the proposed regional approach. The circuit level design directly calculates and determines the size of on-chip decoupling capacitors, the size and the location of off-chip decoupling capacitors, and the effective inductances of the package power bus. As a design output, a lumped circuit model and a pre-layout of the power bus including a whole decoupling capacitors are obtained after processing FAPUD. In the tuning procedure, the board re-optimization considering simultaneous switching noise (SSN) added by I/O switching can be carried out because the I/O switching effect on a power supply noise can be estimated over the operation frequency range with the lumped circuit model. Furthermore, if a design changes or needs to be tuned, FAPUD can modify design by replacing decoupling capacitors without consuming other design resources. Finally, FAPUD is accurate compared with conventional PEEC-based design tools, and its design time is 10 times faster than that of conventional PEEC-based design tools.

Currant Source GTO Inverter with Double Recovery Path of Commutation Energy by LCD (수동소자에 의한 축적에너지 2중 궤환방식 전류형 GTO 인버터의 입.출력 특성)

  • Kim, Jin-Pyo;Choi, Sang-Won;Lee, Jong-Ha
    • Proceedings of the KIEE Conference
    • /
    • 1997.07f
    • /
    • pp.2104-2106
    • /
    • 1997
  • In order to develop the three phase GTO CSI with double recovery path of commutation energy by passive devices (LCD), we studied the clamping circuit to protect switching device and energy recovery circuit to recover absorbed energy of capacitor and DC inductor. In this paper, we investigated how DC input power is increased or decreased according to energy recovery path with or not in the three phase GTO current source inverter, we used a induction motor as inverter load, and controlled a induction motor with v/f constant control. Experimental results show that dissipated DC power is decreased in $9{\sim}14%$ by double recovery path. We also confirmed that the characteristics is met as compare simulation results with experimental results according to each frequency.

  • PDF

The Characteristics of New Current Source GTO Inverter with Double Recovery Path of Commutation Energy (전류(轉流)에너지 2중 궤환방식 새로운 전류형 GTO 인버터의 특성)

  • Choi, Sang-Won;Kim, Jin-Pyo;Lee, Jong-Ha
    • Proceedings of the KIEE Conference
    • /
    • 1997.11a
    • /
    • pp.435-437
    • /
    • 1997
  • In order to develop the three phase GTO CSI with double recovery path of commutation energy by passive devices (LCD), we studied the clamping circuit to protect switching device and energy recovery circuit to recover absorbed energy of capacitor and DC link inductor. In this paper, we investigated how DC input power is increased or decreased according to energy recovery path with or not in the three phase GTO current source inverter. We used a induction motor as the load of inverter, and controlled a induction motor with V/F constant control. Experimental results show that dissipated DC power is decreased and capacitor voltage Vc is effectively suppressed by double recovery path.

  • PDF

Effect of Channel Variation on Switching Characteristics of LDMOSFET

  • Lee, Chan-Soo;Cui, Zhi-Yuan;Kim, Kyoung-Won
    • Journal of Semiconductor Engineering
    • /
    • v.3 no.2
    • /
    • pp.161-167
    • /
    • 2022
  • Electrical characteristics of LDMOS power device with LDD(Lightly Doped Drain) structure is studied with variation of the region of channel and LDD. The channel in LDMOSFET encloses a junction-type source and is believed to be an important parameter for determining the circuit operation of CMOS inverter. Two-dimensional TCAD MEDICI simulation is used to study hot-carrier effect, on-resistance Ron, breakdown voltage, and transient switching characteristic. The voltage-transfer characteristics and on-off switching properties are studied as a function of the channel length and doping levels. The digital logic levels of the output and input voltages are analyzed from the transfer curves and circuit operation. Study indicates that drain current significantly depends on the channel length rather than the LDD region, while the switching transient time is almost independent of the channel length. The high and low logic levels of the input voltage showed a strong dependency on the channel length, while the lateral substrate resistance from a latch-up path in the CMOS inverter was comparable to that of a typical CMOS inverter with a guard ring.

Performance Analysis about the Failure Restoration Scheme Using a Multi-path in Hierarchical MPLS Networks (계층형 MPLS 네트워크에서 다중 경로를 이용한 장애 복구 방안에 관한 성능 분석)

  • Jang, Seong-Jin;Kim, Ki-Yong;Jang, Jong-Wook
    • Proceedings of the Korean Institute of Information and Commucation Sciences Conference
    • /
    • 2007.06a
    • /
    • pp.61-64
    • /
    • 2007
  • MPLS networks architectures have been prevailed as scalable approach to provide quality of service in the Internet. Many researches have been mainly focused on scalability and multi-path calculation scheme for failure restoration. However, the MPLS network have an scalability problem about traffic, and the existing failure restoration methods are wasted resources, and it has the problem that loss of a packet by a lot of delay occurs in too. Therefore in this paper, we propose a H-MPLS (Hierachical-Multiprotocol Label Switching)network for rapidly failure restorations and effective management of network extended. The proposed H-MPLS Network apply LSP multi-path routing algorithm and consists of several MPLS. After comparing the performance among the existing failure restoration methods with various network models, we use NS simulator in order to analyze the performance. Finally, we present an improvement scheme of the efficiency and scalability.

  • PDF

Packet Lossless Fast Rerouting Scheme without Buffer Delay Problem in MPLS Networks (MPLS망에서 버퍼지연 문제가 발생하지 않는 무손실 Fast Rerouting 기법)

  • 신상헌;신해준;김영탁
    • Journal of KIISE:Information Networking
    • /
    • v.31 no.2
    • /
    • pp.233-241
    • /
    • 2004
  • In this paper, we propose a packet-lossless fast rerouting scheme at a link/node fault in MPLS (Multiprotocol Label Switching) network with minimized accumulated buffer delay problem at ingress node. The proposed scheme uses a predefined, alternative LSP (Label Switched Path) In order to restore user traffic. We propose two restoration approaches. In the first approach, an alternative LSP is initially allocated with more bandwidth than the protected working LSP during the failure recovery phase. After the failure recovery, the excessively allocated bandwidth of the alternative LSP is readjusted to the bandwidth of the working LSP. In the second approach, we reduce the length of protected working LSP by using segment-based restoration. The proposed approaches have merits of (ⅰ) no buffer delay problem after failure recovery at ingress node, and (ⅱ) the smaller required buffer size at the ingress node than the previous approach.

Load Balancing in MPLS Networks (MPLS 네트워크에서의 부하 분산 방안)

  • Kim, Sae-Rin;Song, Jeong-Hwa;Lee, Mee-Jeong
    • The KIPS Transactions:PartC
    • /
    • v.9C no.6
    • /
    • pp.893-902
    • /
    • 2002
  • MPLS enables efficient explicit routing, and thus provides great advantages in supporting traffic engineering. Exploiting this capability, we Propose a load balancing scheme which deploys a multipath routing. It is named LBM (Load Balancing in MPLS networks), and targets at efficient network utilization as well as performance enhancement. LBM establishes multiple LSP (Label Switched Path)s between a pair of ingress-egress routers, and distributes traffic over these LSPs at the new level. Its routing decision is based on both the length and the utilization of the paths. In order to enhance the efficiency of a link usage, a link is limited to be used by shorter paths as its utilization becomes higher Longer paths are considered to be candidate alternative paths as the utilization of shorter paths becomes higher. Simulation experiments are performed in order to compare the performance of LBM to that of static shortest path only scheme as well as the other representative dynamic multipath traffic distribution approaches. The simulation results show that LBM outperforms the compared approaches, and the performance gain is more significant when the traffic distribution among the ingress-egress pairs is non-uniform.

Impact of Switchover Barrier, Switchover Intention and Willingness to Revisit on Customer's Characteristics - Comparison between Travel Agency and Airlines - (고객특성이 전환장벽, 전환의도와 재방문의사에 미치는 영향 - 여행사.항공사간 비교분석을 중심으로 -)

  • Chung, Ung-Young;Moon, Hye-Young
    • The Journal of the Korea Contents Association
    • /
    • v.8 no.9
    • /
    • pp.259-273
    • /
    • 2008
  • This study aims to identify of customer features control the effect on revisit intention and switching intention. The statistical techniques used for this empirical analysis are frequency analysis, technology analysis, reliability analysis, factor analysis, confirmatory factor analysis along with path analysis and moderate regression analysis, which are based on structural model From the effect that customer features control the effect on switching barrier by switching intention, travel agencies has a control effect on 'financial switching costs' and 'relational switching costs', and airlines show they have control effect on 'relational switching costs.' In diversity pursuit factors, 'financial switching costs' and 'attractiveness of alternatives' have a meaningful control effect for travel agencies customers, while 'procedural switching costs' for airlines customers. In the analysis result of the effect that customer features control the effect on revisit intention by switching intention, 'percept' and 'diversity pursuit' have a meaningful control effect in travel agencies customers and airlines one, respectively.