• 전자공학회논문지A
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• 제30A권3호
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• pp.139-145
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• 1993

Partitioning is an important step in the hierarchical design of very large scale integrated circuits. In this research, a new effective partitioning algorithm based on 2-level hierarchy is presented. At the beginning, clusters are formed to reduce the problem size. To overcome the weakness of the iterative improvement techniques that the partitioning result is dependent on the initial partitioning and to consistently produce good results, the cluster-level partitioning is performed several times using several sets of parameters. Then the best result of cluster-partitioning is used as the initial solution for lower level partitioning. For each partitioning, the gradual constraint enforcing partitioning method has been used. The clustering-based partitioning algorithm has been applied to several benchmark examples and produced promising results which show that this algorithm is efficient and effective.

• 한국국방경영분석학회지
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• 제22권1호
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• pp.81-96
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• 1996

In a relational database environment, partitioning of data is directly concerned with the amount of data that needs to be required in a query or transaction. In this paper, we consider non-overlapping, vertical partitioning. Vertical partitioning algorithm in this paper is composed of two phases. In phase 1, we cluster the attributes with zero-one integer program that maximize affinity among attributes. The result of phase 1 is called 'Initial Fragments'. In phase 2, we modify Initial Fragments that is not directly considered by cost factors, making use of a transaction-based partitioning method. A transaction-based partitioning method is partitioning attributes according to a set of transactions. In this phase we select logical accesses which needs to be required in a transaction as comparison criteria. In phase 2, proposed algorithm consider only small number of modification of Initial Fragments in phase 1. This algorithm is so insensible to number of transactions and of attributes that it can applied to relatively large problems easily.

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2004년도 하계종합학술대회 논문집(2)
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• pp.553-556
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• 2004

In this paper, we present a new efficient multi-level hardware/software partitioning algorithm for system-on-a-chip design. Originally the multi-level partitioning algorithm are proposed to enhance the performance of previous iterative improvement partitioning algorithm for large scale circuits. But when designing very complex and heterogeneous SoCs, the HW/SW partitioning decision needs to be made prior to refining the system description. In this paper, we present a new method, based on multi-level algorithm, which can cover SoC design. The different variants of algorithm are evaluated by a randomly generated test graph. The experimental results on test graphs show improvement average $9.85\%$ and $8.51\%$ in total communication costs over FM and CLIP respectively.

• 전자공학회논문지A
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• 제29A권4호
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• pp.91-98
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• 1992

In this paper, a new heuristic algorithm for designing combinational circuits suitable for verification testing is presented. The design method consists of argument reduction, input partitioning, output partitioning, and logic minimization. A new heuristic algorithm for input partitioning and output partitioning is developed and applied to designing combinational circuits to demonstrate its effectiveness.

• 융합신호처리학회논문지
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• 제2권4호
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• pp.97-102
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• 2001

CAD(Computer-Aided Design)에서의 분할(partitioning)은 기능의 최적화를 위해 대상의 그룹화(grouping)로 레이아웃(layout)에 면적과 전파지연 최소화를 위해 함께 위치할 소자를 결정하는 문제 또는 스케쥴링이나 유닛 선택을 위한 HLS(high level synthesis)에서의 변수나 연산에 대한 집단화 (clustering) 문제들을 포함하여 분할 문제에서 해를 얻기 위해 Kernighan-Lin 알고리즘 Fiduccia Mattheyses heuristic, 시뮬레이티드 어닐링(simulated annealing)등의 방식이 이용된다. 본 논문에서는 회로 분할 문제에 대하여 유전 알고리즘(GA; genetic algorithm)을 이용한 해 공간 탐색(soultion space search)방식을 제안하였으며, 제안한 방식을 시뮬레이티드 어닐링 방식과 비교, 분석하였다.

• 전자공학회논문지C
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• 제35C권4호
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• pp.1-10
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• 1998

Partitioning problem of large combinational logic has been studied in real world. Most of logic include undectable faults from the structure of it's redundant, fan-out-reconvergent, and symetrical feature. BPT algorithm is proposed to enhance the fault voverage for combinational logic partitioning. This algorithm partitions the logic by cut the lines related to undetectable structure when seperating. Controllability and observability are considered in the process of partitioning. This algorithm is evaluated effective by testing ISCAS85 circuits.

• 한국콘텐츠학회논문지
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• 제21권7호
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• pp.164-170
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• 2021

VLSI 설계에서의 분할(partitioning)은 기능의 최적화를 위하여 설계하고자 하는 회로의 그룹화(grouping)하는 단계로서 레이아웃(layout)에서 면적과 전파지연의 최소화를 위해 함께 배치할 소자를 결정하는 문제이다. 이러한 분할 문제에서 해를 얻기 위해 사용되는 알고리즘은 Kernighan-Lin 알고리즘, Fiduccia Mattheyses heuristic, 시뮬레이티드 어닐링, 유전자 알고리즘 등의 방식이 이용된다. 본 논문에서는 회로 분할 문제에 대하여 유전자 알고리즘과 확률 진화 알고리즘을 결합한 어댑티드 유전자 알고리즘을 이용한 해 공간 탐색(solution space search) 방식을 제안하였으며, 제안한 방식을 유전자 알고리즘 및 시뮬레이티드 어닐링 방식과 비교, 분석하였고, 어댑티드 유전자 알고리즘이 시뮬레이티드 어닐링 및 유전자 알고리즘보다 더 효과적으로 최적해에 근접하는 것을 알 수 있었다.

• Structural Engineering and Mechanics
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• 제14권6호
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• pp.625-647
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• 2002

Parallel execution of computational mechanics codes requires efficient mesh-partitioning techniques. These mesh-partitioning techniques divide the mesh into specified number of submeshes of approximately the same size and at the same time, minimise the interface nodes of the submeshes. This paper describes a new mesh partitioning technique, employing Genetic Algorithms. The proposed algorithm operates on the deduced graph (dual or nodal graph) of the given finite element mesh rather than directly on the mesh itself. The algorithm works by first constructing a coarse graph approximation using an automatic graph coarsening method. The coarse graph is partitioned and the results are interpolated onto the original graph to initialise an optimisation of the graph partition problem. In practice, hierarchy of (usually more than two) graphs are used to obtain the final graph partition. The proposed partitioning algorithm is applied to graphs derived from unstructured finite element meshes describing practical engineering problems and also several example graphs related to finite element meshes given in the literature. The test results indicate that the proposed GA based graph partitioning algorithm generates high quality partitions and are superior to spectral and multilevel graph partitioning algorithms.

• 한국정보과학회논문지:시스템및이론
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• 제26권12호
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• pp.1548-1555
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• 1999

본 논문에서는 하이퍼그래프의 {{{{k분 분할을 위한 서열화(vertex ordering) 알고리즘의 효율을 개선하기 위한 후처리 알고리즘인 재서열법을 소개한다. 제안된 알고리즘은 {{{{k분 분할을 위한 다양한 알고리즘에 쉽게 적용될 수 있다. 보통 초기 분할은 서열화를 기반으로 하는 알고리즘에 의해 형성된다. 그 후 제안된 알고리즘은 클러스터와 정점을 재배열하여 분할하는 과정을 반복함으로써 분할의 효율을 향상시켜간다. 이 방법을 여러 가지 그래프에 적용하여 향상된 결과를 얻었다.Abstract This paper addresses the post-processing algorithm for {{{{k-way hypergraph partitioning by using a cluster and vertex reordering method. The proposed algorithm applies to several {{{{k-way partitioning algorithm. Generally, the initial partition generating method is based on a vertex ordering algorithm. Our reordering algorithm construct an enhanced partitioning by iteratively partition the reodered clusters and vertices. Experimental results on several graphs demonstrate that reodering provides substantial enhancement.

• 한국산업융합학회 논문집
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• 제4권1호
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• pp.87-94
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• 2001

In multibody dynamics, differential and algebraic equations which can satisfy both equation of motion and kinematic constraint equation should be solved. To solve this equation, coordinate partitioning method and constraint stabilization method are commonly used. The coordinate partitioning method divides the coordinate into independent and dependent coordinates. The most typical coordinate partitioning method arc LU decomposition, QR decomposition, projection method and SVD(sigular value decomposition).The objective of this research is to find a efficient coordinate partitioning method in flexible multibody systems and a hybrid decomposition algorithm which employs both LU and projection methods is proposed. The accuracy of the solution algorithm is checked with a slider-crank mechanism.