• Journal of Korea Society of Industrial Information Systems
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• v.9 no.2
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• pp.17-22
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• 2004

In this paper, a concatenated RS and Turbo code is proposed for OFDM system over burst error channel. The concatenated code used in this study is a RS(255,202) code and a rate 1/2 turbo code. The turbo code uses 2 recursive systematic convolutional (RSC) code as the constituent codes and the parity bit are punctured to get the desired code rate. It is shown by simulation that the conventional OFDM system fails when there exists burst noise. The concatenated RS and turbo code obtains at least 5dB gain over the turbo code at the bit error probability of 10/sup -3/.

• Proceedings of the Korean Society of Broadcast Engineers Conference
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• 2009.11a
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• pp.25-27
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• 2009

1962년 R.G Gallager가 제안한 LDPC(Low Density Parity Check)부호는 Shannon의 채널 용량의 한계에 근접한 우수한 오류정정 부호이다. 우수한 LDPC부호 생성 조건 중 가장 중요한 부분은 바로 최소 사이클 길이(girth)를 최대화 하는 과정인데, PEG(Progressive Edge Growth)알고리듬은 이 조건을 만족시키는 우수한 알고리듬으로 인정받고 있다. 이후 높은 SNR범위에서 PEG알고리듬의 성능을 개선한 IPEG (Improved PEG) 알고리듬을 포함한 다양한 알고리듬이 제안 되었다.본 논문은 PEG와 IPEG 알고리듬을 이용해 생성한 LDPC 부호를 이용하여 부호길이, 부호율을 변화시키면서 실험하여 그 결과를 비교 분석하였고, 더 좋은 성능을 가질 수 있는 알고리듬에 대해 논의한다.

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.12
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• pp.1792-1799
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• 1990

Two cases of block coded phase/frequncy modulations are investigated. minimum Euclidean distances are calculated as the function of modulation index h and rotation angle \ulcorner in the cases of 2-FSK/4-PSK and 2-FSK/8-PSK. Method of signal set partitioning is described, especially for the case of 2-FSK/8-PSK. The results are compared with S.I. Sayegh's work and shown better performance. For example, with simple parity check and repetition codes, we can get coding gain of 3 dB in the case of 2-FSK/4-PSK with block length n=4. We get 5.33 dB in the case of 2-FSK/8-PSK with n=4. And it is believed that we can get higher coding gain with proper combinations of block code and n-FSK/m-PSK type channel signal constellations.

• KSII Transactions on Internet and Information Systems (TIIS)
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• v.12 no.8
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• pp.3749-3768
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• 2018

As one of the most potential types of low-density parity-check (LDPC) codes, CPM-QC-LDPC code has considerable advantages but there still exist some limitations in practical application, for example, the existing decoding algorithm has a low convergence rate and a high decoding complexity. According to the structural property of this code, we propose a new method based on a CPM-RID decoding algorithm that decodes block-by-block with weights, which are obtained by neural network training. From the simulation results, we can conclude that our proposed method not only improves the bit error rate and frame error rate performance but also increases the convergence rate, when compared with the original CPM-RID decoding algorithm and scaled MSA algorithm.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.36 no.8C
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• pp.522-528
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• 2011

The iterative detection and decoding (IDD) has been shown to dramatically improve the bit error rate (BER) performance of the multiple-input multiple-output (MIMO) communication systems. However, these techniques require a high computational complexity since it is required to compute the soft decisions for each bit. In this paper, we show IDD comprised of sphere decoder with low-density parity check (LDPC) codes and present the tree search strategy, called a layer symbol search (LSS), to obtain soft decisions with a low computational complexity. In addition, an adaptive early termination is proposed to reduce the computational complexity during an iteration between an inner sphere decoder and an outer LDPC decoder. It is shown that the proposed approach can achieve the performance similar to an existing algorithm with 70% lower computational complexity compared to the conventional algorithms.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.19 no.10
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• pp.2367-2372
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• 2015

One of various low-density parity-check(LDPC) codes that has been adopted in many communication standards due to its error correction ability is a quasi-cyclic LDPC(QC-LDPC) code, which leads to comparable decoder complexity. One of the main blocks in the QC-LCDC code decoder is a multi-size circular shifter(MSCS) that can perform various size rotation. The MSCS can be implemented with many structures, one of which is based on Banes network. The Benes network structure can perform the normal MSCS operation efficiently, but it cannot use the properties coming from specifications like rotation sizes. This paper proposesd a scheme where the Benes network structure can use the rotation size property with the modification of the control signal generation. The proposed scheme is applied to the MSCS of IEEE 802.16e WiMAX QC-LDPC decoder to reduce the number of MUXes and the critical path delay.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.35 no.3C
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• pp.255-263
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• 2010

In this paper, we present an efficient cooperative transmission scheme for high speed 60GHz WPAN system. In 60GHz, the cooperative transmission with relay is effective scheme because signals are exceedingly attenuated according to the distance and the transmission is impossible when there is no LOS between transmitter and receiver. Moreover, the reliability of signal in destination can be improved by receiving data from a relay as well as a transmitter. However, the overall data rate is reduced because transmission time is more required for relay. To solve this problem, we propose a cooperative transmission scheme with RS-CC serial concatenated codes. In the proposed cooperative transmission scheme, the relay can reduce the transmission data size because the only parity bits of systematic RS code are transmitted after encoding by CC. But the computational complexity is increased at the relay and the destination.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.38A no.9
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• pp.750-758
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• 2013

In this paper, we introduce the low-density parity-check (LDPC) coded orthogonal frequency division multiplexing (OFDM) subframe reordering scheme for achieving equal combined power allocation in type I hybrid automatic repeat request (H-ARQ) systems and analyze the performance improvement by using the channel capacity. Also, it is confirmed that the layered decoding for subframe reordering scheme in H-ARQ systems gives faster convergence speed. It is verified from numerical analysis that a subframe reordering pattern having larger channel capacity shows better bit error rate (BER) performance. Therefore the subframe reordering pattern achieving equal combined power allocation for each subframe maximizes the channel capacity and outperforms other subframe reordering patterns. Also, it is shown that the subframe reordering scheme for achieving equal combined power allocation gives better performance than the conventional Chase combining scheme without increasing the decoding complexity.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.48 no.1
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• pp.22-30
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• 2011

In this paper, we propose a memory efficient multi-rate Low Density Parity Check (LDPC) decoder for China Mobile Multimedia Broadcasting (CMMB). We find the best trade-off between the performance and the circuit area by designing a partially parallel decoder which is capable of passing multiple messages in parallel. By designing an efficient address generation unit (AGU) with an index matrix, we could reduce both the amount of memory requirement and the complexity of computation. The proposed regular LDPC decoder was designed in Verilog HDL and was synthesized by Synopsys' Design Compiler using Chartered $0.18{\mu}m$ CMOS cell library. The synthesized design has the gate size of 455K (in NAND2). For the two code rates supported by CMMB, the rate-1/2 decoder has a throughput of 14.32 Mbps, and the rate-3/4 decoder has a throughput of 26.97 Mbps. Compared with a conventional LDPC for CMMB, our proposed design requires only 0.39% of the memory.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.39 no.3
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• pp.125-131
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• 2002

In this paper, a new concatenation scheme of serial concatenated convolutional codes is proposed and the performance analyzed. In the proposed scheme, each of information and parity bits of outer code is entered into inner code through interleaver and deinterleaver. Therefore, the interleaver size is same as the length of input frame. Since the interleaver size of proposed type is reduced to half of the conventional Benedetto type, the interleaver delay time required for iterative decoding is reduced. In addition the multiplexer and demultiplexer are not used in the decoder of the proposed type, the complexity of decoder can be also reduced. As results of simulation, the performance of proposed type shows the better error performance as compared to that of the conventional Benedetto type in case of the same interleaver size. And it can be observed that the difference of BER performance is increased with the increase of Eb/No. In case of the same length of input frame, the proposed type shows almost same performance with Benedetto type despite that the interleaver size is reduced by half.