• Journal of Power Electronics
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• 제18권4호
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• pp.1255-1267
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• 2018

Parasitic parameters have a larger influence on Silicon Carbide (SiC) devices with an increase of the switching frequency. This limits full utilization of the performance advantages of the low switching losses in high frequency applications. By combining a theoretical analysis with a experimental parametric study, a mathematic model considering the parasitic inductance and parasitic capacitance is developed for the basic switching circuit of a SiC MOSFET. The main factors affecting the switching characteristics are explored. Moreover, a fast-switching double pulse test platform is built to measure the individual influences of each parasitic parameters on the switching characteristics. In addition, guidelines are revealed through experimental results. Due to the limits of the practical layout in the high-speed switching circuits of SiC devices, the matching relations are developed and an optimized layout design method for the parasitic inductance is proposed under a constant length of the switching loop. The design criteria are concluded based on the impact of the parasitic parameters. This provides guidelines for layout design considerations of SiC-based high-speed switching circuits.

• 전자공학회논문지
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• 제52권10호
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• pp.33-46
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• 2015

본 논문에서는 ITRS(International Technology Roadmap for Semiconductors)를 따라 스케일 다운된 FinFET 소자의 디지털 및 아날로그 회로의 성능을 예측했다. 회로 성능의 정확한 예측을 위해 기생 커패시턴스와 기생 저항 모델을 개발해 3D Technology CAD 해석 결과와 비교해 오차를 2 % 미만으로 달성했다. 기생 커패시턴스 모델은 conformal mapping 방식을 기반으로 모델링 되었으며, 기생 저항 모델은 BSIM-CMG에 내장된 기생 저항 모델을 핀 확장 영역 구조 변수($L_{ext}$) 변화에 따른 기생 저항 성분 변화를 반영 할 수 있도록 개선했다. 또한, 공정 단위 변화에 대해 소자의 전압전류의 DC 특성을 반영하기 위해 BSIM-CMG 모델의 DC 피팅을 진행하는 알고리즘을 개발했다. BSIM-CMG에 내장된 기생 모델을 본 연구에서 개발한 저항과 커패시턴스 모델로 대체해 압축 모델 내부에 구현하여, SPICE 시뮬레이션을 통해 스케일 다운된 FinFET 소자의 $f_T$, $f_{MAX}$, 그리고 링 오실레이터와 공통 소스 증폭기의 기생 성분으로 인한 특성변화를 분석했다. 정확한 기생 성분 모델을 적용해 5 nm FinFET 소자까지 회로 특성을 정량적으로 제시했다. 공정 단위가 감소함에 따라 소자의 DC 특성이 개선될 뿐만 아니라 기생 성분의 영향이 감소하여, 회로 특성이 향상됨을 예측했다.

• 한국정보디스플레이학회:학술대회논문집
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• 한국정보디스플레이학회 2007년도 7th International Meeting on Information Display 제7권2호
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• pp.1607-1610
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• 2007

The measurement technology of the electrical and optical properties of CCFL and EEFL for LCD-BLU is investigated. The lamp current and voltage are affected by the leakage of parasitic capacitance. The methods using the photometer and the integrating sphere are compared to determine the lamp efficiency.

• 조명전기설비학회논문지
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• 제28권3호
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• pp.32-43
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• 2014

This paper presents the intra capacitance modeling according to the winding method, section bobbin and coil structure for hybrid choke coil capable of the EMI attenuation of broad bands from lower frequency bands to higher frequency bands and high frequency type common-mode choke coil capable of the EMI attenuation of high frequency band used in the EMI Block of LED-TV SMPS. In case of high frequency type CM choke coil, it can be explained the parasitic capacitance of A type and section bobbin type winding methods among them is much smaller than the other. The first resonant frequency of the proposed CM choke coil tends to increase as the parasitic capacitance becomes small and its impedance characteristics also show improved performance as the first resonant frequency increases. In case of hybrid choke coil using rectangular copper wire, it has investigated its parasitic capacitance compared to CM choke coil of conventional toroidal type becomes small. Also it has confirmed through the experiment results that CE margin and RE margin in frequency bands 0.5MHz to 5MHz and 30MHz to 200MHz are respectively 10dB and 15dB greater than that of conventional type in case of one stage EMI filter structure adopting hybrid choke coil compared to two stage EMI Filter structure using two of each CM choke coil used in the lower and higher frequency bands or two of CM choke coil used in only the lower frequency bands. In the future, the hybrid choke coil and CM choke coil of high frequency type show it can be practically used in not only LED/LCD-TV SMPS but also several applications such as LED Lighting, Laptop Adapter, Server Power Supply and so on.

• Journal of international Conference on Electrical Machines and Systems
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• 제2권1호
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• pp.57-64
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• 2013

The functional characteristic of LISN circuit, which is used for measurements of conductive noise in mains power line, is basically related to frequency characteristics of passive elements like inductors used in the circuit as well as the frequency response of inductors is highly related to the resins used in the varnishing process. The significant problem in determination of an inductor's frequency characteristic is the intrinsic resistance, inductance and parasitic capacitance. In this triplet, the parasitic capacitance is the major limiting factor of inductor's frequency range. This capacitance depends on inductor design parameters and materials filling the spaces of coil like resin and its coherency after curing process. In this paper, two similar inductors were designed and built. The first inductor was not varnished while the second one was varnished with VPI technology. VPI, or Vacuum, Pressure, Impregnation technology is one of the most reliable methods performing good insulating conditions for electrical circuits and windings based on resins. The measured results show that implying varnishing technology does not significantly affect the frequency response. However, due to mechanical solidity aspects and improved environmental protection, it is better to varnish the inductors.

• 전력전자학회논문지
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• 제19권1호
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• pp.8-14
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• 2014

This paper presents the intra capacitance modeling according to the winding method and section bobbin for CM choke capable of the EMI attenuation of broad bands from lower frequency bands to higher frequency bands and high frequency type common-mode choke capable of the EMI attenuation of high frequency band used in the EMI Block of LED-TV SMPS. In case of high frequency type CM choke, it can be explained the parasitic capacitance of A type and section bobbin type winding methods among them is much smaller than the other. The first resonant frequency of the proposed CM choke tends to increase as the parasitic capacitance becomes small and its impedance characteristics also show improved performance as the first resonant frequency increases. In the future, the CM chokes of high frequency type show it can be practically used in not only LED/LCD-TV SMPS but also several applications such as LED Lighting, Adapter and so on.

• 전력전자학회:학술대회논문집
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• 전력전자학회 2000년도 전력전자학술대회 논문집
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• pp.1-5
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• 2000

This paper deals with the modeling and analysis of the high voltage flyback transformer (HVFBT) often utilized in small-sized high voltage DC power supplies. The parasitic capacitance of th HVFBT with the large turns of the secondary winding causes the undesirable parasitic resonance in the transient state which produces the high current stress and limits the switching frequency of the converter. In order to analyze this phenomenon the equivalent circuit model including the parasitic capacitance is derived and the frequency characteristics are provided. The parasitic resonance in the switching states is also investigated based on this equivalent circuit model. The derived model and analysis is finally validated through the SPICE simulation and experiments.

• 대한전자공학회논문지
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• 제25권1호
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• pp.101-107
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• 1988

This paper proposes a circuit extractor which extracts a netlist from the CIF input file cntaining the layout mask artwork informations. The circuit extractor extracts transistors and their interconnections, and calculates circuit parameter such as parasitic resistance and parasitic capacitance from the mask informations. When calculating the parasitic resistance, we consider the current flow path to reduce the errors caused by the resistance approximation. Similarly, we consider the coupling capacitance which has an effect on the circuit characteristics, when the parasitic capacitances are calculated. Therefore, using these parameter values as an input to circuit simulation, the circuit characteristics such as delay time can be estimated accurately. The presented circuit extraction algorithm uses a multiple storage quad tree as a data sturucture for storing and searching the 2-dimensional geometric data of mask artwork. Also, the proposed algorithm is technologically independent to work across a wide range of MOS technologies without any change in the algorihm.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2005년도 춘계학술대회 논문집 전기기기 및 에너지변환시스템부문
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• pp.55-57
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• 2005

This paper deals with the analysis of bearing current in H-bridge seven level multilevel inverter fed induction motor. In the previous researches utilized electromagnetic equations to derive the parasitic capacitance or measured capacitance parameters, but we used FEM to derive parasitic capacitances and defined the equivalent circuit parameters in our strategy. Then we compared suggested method with conventional method in 60 [Hz] no load condition.

• 대한전자공학회논문지SD
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• 제37권7호
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• pp.7-16
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• 2000

본 논문에서는 DRAM 셀 내의 셀 캐패시턴스 및 기생 캐패시턴스를 수치 해석적으로 계한하여 추출하는 방법과 그 적용 예를 보고한다. 셀 캐패시턴스 및 기생 캐패시턴스를 계산하기 위하여 유한요소법을 적용하였다. 시뮬레이션의 구조를 정의하기 우하여, 마스크 레이아웃 데이터 및 공정 레시피를 이용한 토포그래피 시뮬레이션을 수행하고, 토포그래피 시뮬레이션을 통해 DRAM 셀 구조를 생성하기 위해 필요한 데이터를 얻었다. 이를 기반으로 하여, 마스크 데이터 기반의 3차원 솔리드 모델링 방법을 적용하여 시뮬레이션 구조를 생성하였다. 시뮬레이션에 사용된 구조는 $2.25{\times}175{\times}3.45{\mu}m^3$ 크기이며, 4개의 셀 캐패시터를 갖는다. 또한 70,078개의 노드와 395,064개의 사면체로 구성되었다. 시뮬레이션을 위해 ULTRA SPARC 10 웨크스테이션에서 약 25분의 CPU 시간을 소요하였으며, 약 201메가바이트의 메모리를 사용하였다. 시뮬레이션을 통하여 계산된 셀 캐패시턴스는 셀당 24fF이며, DRAM 셀 내에서 가장 주요한 기생 캐패시턴스 성분을 규명하였다.