• Journal of Korea Society of Industrial Information Systems
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• v.21 no.1
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• pp.1-6
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• 2016

In this paper, we introduce the characteristics of a vertical PNP transistor that improves start current by decreasing quiescent current with suppressing the parasitic transistor. In order to suppress the parasitic effect, we designed a vertical PNP transistor which suppresses parasitic PNP transistor by using the "DN+ links" without changing the circuit and made a LDO regulator using a standard IC processor. HFE of the fabricated parasitic PNP transistor decreased from conventional 18 to 0.9. Starting current of the LDO regulator made of the vertical PNP transistor using the improved "DN+ linked" structure is reduced from the conventional starting current of 90mA to 32mA. As the result, we developed a LDO regulator which consumes lower power in the standby state.

• JSTS:Journal of Semiconductor Technology and Science
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• v.17 no.3
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• pp.401-410
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• 2017

In this work, we show that the excessive lattice heating problem due to parasitic pnp transistor action in the diode electrostatic discharge (ESD) protection device in the diode input protection circuit, which is favorably used in CMOS RF ICs, can be solved by adopting a symmetrical cathode structure. To explain how the recipe works, we construct an equivalent circuit for input human-body model (HBM) test environment of a CMOS chip equipped with the diode protection circuit, and execute mixed-mode transient simulations utilizing a 2-dimensional device simulator. We attempt an in-depth comparison study by varying device structures to suggest valuable design guidelines in designing the protection diodes connected to the $V_{DD}$ and $V_{SS}$ buses. Even though this work is based on mixed-mode simulations utilizing device and circuit simulators, the analysis given in this work clearly explain the mechanism involved, which cannot be done by measurements.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.47 no.2
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• pp.40-50
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• 2010

The studies of PMOS transistors in CMOS technologies are reviewed- focusing on the snapback and breakdown behavior of the parasitic PNP BJTs in high current regime. A new failure mechanism of PMOSFET devices under ESD conditions is also analyzed by investigating various I/O structures in a $0.13\;{\mu}m$ CMOS technology. Localized turn-on of the parasitic PNP transistor can be caused by localized charge injection from the adjacent diodes into the body of the PMOSFET, significantly degrading the ESD robustness of PMOSFETs. Based on 2-D device simulations the critical layout parameters affecting this problem are identified. Design guidelines for avoiding this new PMOSFET failure mode are also suggested.