• Proceedings of the KIPE Conference
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• 2007.11a
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• pp.31-33
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• 2007

In this paper, a simple digital control scheme for the single/parallel module buck converters is proposed using a digital state feedback control method. The discrete state feedback controller structure for the robust tracking control is derived by using the error state. The proposed control system can precisely achieve the interleaved current sharing and the output regulation, and can achieve the systematical controller design for a given converter specification using the pole placement technique. For a design example, the single module buck converter is simulated using the MATLAB Simulink software and two 100W parallel module buck converters with a TMS320F2812 DSP is implemented.

• Journal of Mechanical Science and Technology
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• v.18 no.4
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• pp.718-730
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• 2004

The solution for the natural convection in internally finned horizontal annuli is obtained by using a numerical simulation of time-dependent and two-dimensional governing equations. The fins existing in annuli influence the flow pattern, temperature distribution and heat transfer rate. The variations of the On configuration suppress or accelerate the free convective effects compared to those of the smooth tubes. The effects of fin configuration, number of fins and ratio of annulus gap width to the inner cylinder radius on the fluid flow and heat transfer in annuli are demonstrated by the distribution of the velocity vector, isotherms and streamlines. The governing equations are solved efficiently by using a parallel implementation. The technique is adopted for reduction of the computation cost. The parallelization is performed with the domain decomposition technique and message passing between sub-domains on the basis of the MPI library. The results from parallel computation reveal in consistency with those of the sequential program. Moreover, the speed-up ratio shows linearity with the number of processor.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1518-1527
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• 1989

We proposed a technique to design a multimicrocomputer system for real-time parallel processing with an interconnection network which has good network latency time. In order to simplify the performance evaluation and the design procedure under the hard real-time constraints we defined network latency time which takes into account the queueing delays of the networks. We designed a dynamic interconnection network following the proposed technique, and the simulation results show that we can easily estimate the multimicrocomputer system's approximate performance using the defined network latency time before the actual design, so this definition can help the efficient design of the real-time parallel processing systems.

• The Transactions of the Korean Institute of Power Electronics
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• v.20 no.1
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• pp.38-44
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• 2015

This paper presents the sensorless drive method for mono inverter dual parallel (MIDP) surface mounted permanent magnet synchronous motor (SPMSM) drive system. MIDP motor drive system is a technique that can reduce the cost of the multi motor driving system. To maximize this merit of the MIDP motor drive system, the sensorless technique is essential to eliminate the position sensors. This paper adopts an appropriate sensorless method for MIDP SPMSM drive system, which uses the reduced order observer and phase locked loop (PLL) to reduce the calculation burden. The I-F control method is implemented for start-up and low speed operation. The validity and performance of the proposed algorithm are shown via experiments with 600-W SPMSMs.

• JSTS:Journal of Semiconductor Technology and Science
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• v.14 no.3
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• pp.345-355
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• 2014

Today's System-on-a-Chip (SoC) is designed with reusable IP cores to meet short time-to-market requirements. However, the increasing cost of testing becomes a big burden in manufacturing a highly integrated SoC. In this paper, an efficient parallel scan test technique is introduced to minimize the test application time. Multiple scan enable signals are adopted to implement scan architecture to achieve optimal test application time for the test patterns scheduled for concurrent scan test. Experimental results show that testing times are considerably reduced with little area overhead.

• ETRI Journal
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• v.20 no.1
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• pp.16-27
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• 1998

In this paper, we consider the acquisition performance of an IS-95 reverse link access channel slot as a function of system design parameters such as postdetection integration length and the number of access channel message block repetitons. The uncertainty region of the reverse link spreading codes compared to that of forward link is very small, since the uncertainty region of the reverse link is determined by a cell radius. Thus, the parallel acquisiton technique in the reverse link is more efficient than a serial acquisition technique in terms of implementation and of acquisition time. The parallel acquisition is achieved by a bank of N parallel I/Q noncoherent correlator are analyzed for band-limited noise and the Rayleigh fast fading channel. The detection probability is derived for multiple correct code-phase offsets and multipath fading. The probability of no message error is derived when rake combining, access channel message block combining, and Viterbi decoding are applied. Numerical results provide the acquisition performance for system design parameters such as postdetection integration length and number of access channel message block repetitions in case of a random access on a mobile station.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.48 no.7
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• pp.363-368
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• 1999

The parallel operation system of multiple uninterruptible power supplies(UPSs) is used to increase power capacity of the system or to secure higher reliability at critical loads. In the parallel operation of the two UPSs, the load-sharing control to maintain the current balance between them is a key technique. Because a UPS has low output impedance and quick response characteristics, in case of an unbalanced load inverter output current changes very rapidly and thereby can instantaneously reach an overload condition. In this study, high precise load-sharing controller is proposed and implemented for the parallel operation system of two UPSs with low impedance characteristics and this controller controls the frequency and the voltage to minimize the active power component and the reactive power component which are gotten from the current difference between two UPSs. And then a good performance of the proposed method is verified by experiments in the parallel operation system with two 40KVA UPSs.

• 한국전산유체공학회:학술대회논문집
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• 1997.10a
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• pp.23-28
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• 1997

A parallel implementation is made of a two-dimensional finite volume model based on the SIMPLER. The solution domain is decomposed into several subdomains and the solution at each subdomain is acquired by parallel use of multiple processors. Communications between processors are accomplished by using the standard MPI and the Cray-specific SHMEM. The parallelization method for the overall solution procedure to the Navier-Stokes equations is described in detail, The parallel implementation is validated on the Cray T3E system for a benchmark problem of natural convection in a sidewall-heated cavity. The parallel performance is assessed and the issues encountered in achieving a high-performance parallel model are elaborated.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.8
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• pp.2077-2089
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• 1996

In this paper, a memory organization and its control method are proposed for the implementation of parallel Virterbi decoders. The design is mainly focused on lowering the hardware complexity of a parallel Viterbi decoder which is to reduce the decoding speed. The memories requeired in a Viterbi decoder are the SMM(State Metric Memory) and the TBM(Traceback Memory);the SMM for storing the path metrics of states and the TBM for storing the survial path information. A general parallel Viterbi decoder for high datarate usually consists of multiple ACS (Add-Compare-Select) units and their corresponding memeory modules.for parallel ACS units, SMMs and TBMs are partitioned into smaller independent pairs of memory modules which are separately interleaved to provide the maximum processing speed. In this design SMMs are controlled with addrss generators which can simultaneously compute addresses of the new path metrics. A bit shuffle technique is employed to provide a parallel access to the TBMs to store the survivor path informations from multiple ACS modules.

• Journal of Sensor Science and Technology
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• v.24 no.3
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• pp.188-193
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• 2015

This paper presents a new byte-wise BCH (4122, 4096, 2) decoder, which treats byte-wise parallel operations so as to enhance its throughput. In particular, we evaluate the parallel processing technique for the most time-consuming components such as syndrome generator and Chien search owing to the iterative operations. Even though a syndrome generator is based on the conventional LFSR architecture, it allows eight consecutive bit inputs in parallel and it treats them in a cycle. Thus, it can reduce the number of cycles that are needed. In addition, a Chien search eliminates the redundant operations to reduce the hardware complexity. The proposed BCH decoder is implemented with VHDL and it is verified using a Xilinx FPGA. From the simulation results, the proposed BCH decoder can enhance the throughput as 43% and it can reduce the hardware complexity as 67% compared to its counterpart employing parallel processing architecture.