• Journal of the Korean Institute of Telematics and Electronics A
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• v.31A no.4
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• pp.30-38
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• 1994

In this paper, we propose the parallel scrambling technique which is applicable in the multibit-interleaved multiplexing environment. For this, we introduce the concept of SSRG (simple shift register generator) and MSRG(modular shift register generator), and investigate their properties. We also introduce the concept of PSRG(parallel shift register generator) - parallel form of shift register generator, and consider realizations of PSRGs based on SSRGs and MSRGs. Finally, we show how to apply PSRGs to the parallel scrambling for the SDH system.

• The KIPS Transactions:PartA
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• v.8A no.3
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• pp.253-260
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• 2001

It is important to detect races for debugging shared-memoy parallel programs, because the races cause unintended nondeterministic program execution. Previous on-the-fly techniques to detect races can not guarantee the first race detection in nested parallel programs. Detecting the first race is important for debugging parallel programs, since the removal of the first race may make the next occurred races disappear. In this paper, we presents an on-the-fly detection technique to detect all of the first races through the reexecution of the debugged programs. We assume that the debugged parallel program may have one-way nested parallel programs. The number of reexecution is at the least the nesting depth of the program in the worst case. The space complexity is O(VT) and the time complexity to detect race in each access of access history is O(T), where V is number of shared variables and T is the maximum parallelism of the program. This efficiency of our technique in each execution is the same with the previous on-the-fly detection techniques. Therefore, this technique makes debugging parallel programs more effective and practical.

• Proceedings of the KIEE Conference
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• 2007.04a
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• pp.196-198
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• 2007

A circuit design technique to reduce the propagation time is proposed for the analog parallel processing-based Viterbi decoder. The analog Viterbi decoder implements the function of the conventional digital Viterbi decoder utilizing the analog parallel processing circuit technology. The decoder is for the PR(1.2,2.1) signal of DVD. The benefits are low power consumption and less silicon occupation. In this paper, a propagation time reduction technique is proposed by minimizing the parasitic capacitance components in the layout design of the analog Viterbi decoder. The propagation time reduction effect of the proposed technique has been shown via HSPICE simulation.

• Journal of the Korean Institute of Telematics and Electronics B
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• v.33B no.5
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• pp.41-51
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• 1996

In this paper, anew parallel processing system based on a cluster architecture which provides scalability of a parallel processing system while maintains shared memory multiprocessor characteristics is proposed. In recent days low cost, high performnce microprocessors have led to construction of large scale parallel processing systems. Such parallel processing systems provides large scalability but are mainly used for scientific applications which have large data parallelism. A shared memory multiprocessor system like TICOM is currently used as aserver for the commercial application, however, the shared memory multiprocessor system is known to have very limited scalability. The proposed architecture can support scalability and performance of the parallel processing system while it provides adaptability for the commerical application, hence it can overcome the limitation of the shared memory multiprocessor. The architecture and characteristics of the proposed system shall be described. A proprietary hierarchical crsossbar network is designed for this system, of which the protocol, routing and switching technique and the signal transfer technique are optimized for the proposed architecture. The design trade-offs for the network are described in this paper and with simulation usihng the SES/workbench, it is explored that the network fits to the proposed architecture.

• IEMEK Journal of Embedded Systems and Applications
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• v.11 no.1
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• pp.21-27
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• 2016

An integrated display software platform for small UAV is developed based on parallel processing technique in this paper. When the small UAV with high-performance camera and avionic modules is employed to various surveillance-related missions, it is important to reduce the operator's workload and increase the monitoring efficiency. For this purpose, it is needed to develop an efficient monitoring software enable to manipulate the image and flight data obtained during flight within the given processing time and display them simultaneously. In this paper, we set up requirements and suggest the architecture for the software platform. The integrated software platform is implemented with parallel processing scheme. Based on AR drone, we verified that the various data are concurrently displayed by the suggest software platform.

• Journal of Environmental Science International
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• v.15 no.3
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• pp.261-269
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• 2006

In this study, an optimization technique was developed from the application of allocation rule. The results obtained from the water supply analysis and reliability indices analysis of Andong dam and Imha dam which are consist of parallel reservoir system are summarized as the followings; Allocation rule(C) is effective technique at the parallel reservoir system because results of the water supply analysis, storage analysis and reliability indices analysis is calculated reasonable results. Also, reliability indices analysis results are not sufficient occurrence based reliability or quantity based reliability. Thus reliability indices analysis are need as occurrence based reliability, quantity based reliability vulnerability, resilience, average water supply deficits and average storage. And water supply condition is better varying water supply condition than constant water supply condition.

• Journal of the Korean Institute of Illuminating and Electrical Installation Engineers
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• v.14 no.6
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• pp.12-17
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• 2000

IN induction heating system the high frequency operation allows a rapid response to current fluctuation in the inverter and result in improved welding quality. To work induction heating of nonferrous metals, a welding power supply is need high working frequency and high power. This paper is shown design technique for increasing working frequency in induction heating for welding coppers. A series-parallel resonate inverter consists of H-type bridges, each of whose arms is composed of a combination of two parallel IGBTs. Inverter operating with the fixed frequency is controlled by pulse width modulation (PWM). As switching adapted the Zero-Voltage Switching technique to reduce switching losses the system is high efficiency. The propose inverter has feature which is high efficiency for very wide load variations with a narrow range of duty cycle ratio control and load short circuit capability. Detailed experimental results obtained from a 48[V] output, 500[W] experimental inverter are presented to verify the concept.

• Transactions of the Korean Society of Machine Tool Engineers
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• v.13 no.3
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• pp.44-52
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• 2004

This paper proposed a error compensation methodology for three-DOF translational parallel manipulator. The proposed method uses CMM (coordinate measuring machine) as metrology equipment to measure the position of end-effector. To identify the transform relationships between the coordinate system of the parallel manipulator and the CMM coordinate system, a new coordinate referencing (or coordinate system identification) technique is presented. By using this technique, accurate coordinate transformation relationships are efficiently established. According to these coordinate transformation relationships, an equation to calculate the compensating error components at any arbitrary position of the end-effector is derived. In this paper, Monte Carlo simulation method is applied to simulate the compensation process. Through the simulation results, the proposed error compensation method proves its effectiveness and feasibility.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.2
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• pp.383-393
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• 1996

This paper considers the evaluation of the ecquistion performance for an accesschannel preamble based on a random access procedure of direct sequence code division multiple access(DS/CDMA) reverse link. The parallel acquistion technique that employs the single-well detection scheme and the multiple-dwell(double-dwell) detection scheme is mentioned. The acquisition performance for two detection schemes is compared in therms of the acquisition probability and the acquisition time. The parallel acquisition is done by a bank of N parallel I/Q noncoherent correlators. Expressions on the detection, false alarm, and miss probabilities of the single-dwell and multiple-dwell(double-well) detection schemes are derived for multiple H$_{1}$ cells and multipath Rayleight fading channel. comparing the single-dwell detection scheme with the multiple-dwell(double-dwell) detection scheme in the case of employing the parallel acquisition technique in the reverse link,the numerical results show that the single-dwell detection scheme deomonstrates a better performance.

• KIPS Transactions on Computer and Communication Systems
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• v.11 no.6
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• pp.167-174
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• 2022

PIPO lightweight block ciphers were announced in ICISC'20. In this paper, a single-block optimization implementation and parallel optimization implementation of PIPO lightweight block cipher ECB, CBC, and CTR operation modes are performed on a 32-bit RISC-V processor. A single block implementation proposes an efficient 8-bit unit of Rlayer function implementation on a 32-bit register. In a parallel implementation, internal alignment of registers for parallel implementation is performed, and a method for four different blocks to perform Rlayer function operations on one register is described. In addition, since it is difficult to apply the parallel implementation technique to the encryption process in the parallel implementation of the CBC operation mode, it is proposed to apply the parallel implementation technique in the decryption process. In parallel implementation of the CTR operation mode, an extended initialization vector is used to propose a register internal alignment omission technique. This paper shows that the parallel implementation technique is applicable to several block cipher operation modes. As a result, it is confirmed that the performance improvement is 1.7 times in a single-block implementation and 1.89 times in a parallel implementation compared to the performance of the existing research implementation that includes the key schedule process in the ECB operation mode.