• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.3A
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• pp.331-336
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• 2004

This study focuses on the hardware implementation of fast and low-system-complexity multiplier over GF(2$^{m}$ ). From the properties of an irreducible AOP of degree m. the modular reduction in GF(2$^{m}$ ) multiplicative operation can be simplified using cyclic shift operation. And then, GF(2$^{m}$ ) multiplicative operation can be established using the away structure of AND and XOR gates. The proposed multiplier is composed of m(m+1) 2-input AND gates and (m+1)$^2$ 2-input XOR gates. And the minimum critical path delay is Τ$_{A+}$〔lo $g_2$$^{m}$ 〕Τ$_{x}$ proposed multiplier obtained have low circuit complexity and delay time, and the interconnections of the circuit are regular, well-suited for VLSI realization.n.

• Journal of Power Electronics
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• v.11 no.5
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• pp.632-638
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• 2011

This paper presents a cascaded coil flux control based on a Current Source Parallel Resonant Push-Pull Inverter (CSPRPI) for Induction Heating (IH) applications. The most important problems associated with current source parallel resonant inverters are start-up problems and the variable response of IH systems under load variations. This paper proposes a simple cascaded control method to increase an IH system's robustness to load variations. The proposed IH has been analyzed in both the steady state and the transient state. Based on this method, the resonant frequency is tracked using Phase Locked Loop (PLL) circuits using a Multiplier Phase Detector (MPD) to achieve ZVS under the transient condition. A laboratory prototype was built with an operating frequency of 57-59 kHz and a rated power of 300 W. Simulation and experimental results verify the validity of the proposed power control method and the PLL dynamics.

• Journal of Electrical Engineering and Technology
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• v.2 no.3
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• pp.335-341
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• 2007

In this study, we present an approach to parallelizing OPF that is suitable for distributed implementation and is applicable to very large inter-connected power systems. The approach could be used by utilities for optimal economy interchange without disclosing details of their operating costs to competitors. It could also be used to solve several other computational tasks, such as state estimation and power flow, in a distributed manner. The proposed algorithm was demonstrated with several case study systems.

• Proceedings of the KIEE Conference
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• 1987.07b
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• pp.1573-1576
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• 1987

A 4-bit parallel-series A/D converter has been designed using a new matrix circuit and breadboarded with transister array(TPQ2483). The simple matrix circuit is substituted for D/A converter and sebtracter-multiplier. The system has been simulated with SPICE. This converter is capable of operating at clock rate of 20MHz.

• Proceedings of the Korean Society of Computer Information Conference
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• 2018.07a
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• pp.49-50
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• 2018

인공지능의 급격한 발전으로 빅 데이터의 활용이 증가되었지만 이로 인해 머신 러닝에서 일어나는 문제들 또한 해결해야할 과제이다. 본 논문에서는 이에 따라 초래되는 문제들 중 학습 데이터가 많아질 경우의 문제들을 방지하기 위해, 알고리즘의 수정 대신 병렬 처리 기반 시스템을 제안한다. 본 논문에서는 Alternating Direction Method of Multiplier(ADMM) 알고리즘을 소개하고 ADMM 기반의 최적화 기법을 적용하여 병렬 학습 시스템 최적화를 제안하였다.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.41 no.9
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• pp.73-84
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• 2004

This paper suggests a new scalar multiplication algerian to resist SPA which threatens the security of cryptographic primitive on the hardware recently, and discusses how to apply this algerian Our algorithm is better than other SPA countermeasure algorithms aspect to computational efficiency. Since known SPA countermeasure algorithms have dependency of computation. these are difficult to construct parallel architecture efficiently. To solve this problem our algorithm removes dependency and computes a multiplication and a squaring during inversion with parallel architecture in order to minimize loss of performance. We implement hardware logic with VHDL(VHSIC Hardware Description Language) to verify performance. Synthesis tool is Synplify Pro 7.0 and target chip is Xillinx VirtexE XCV2000EFGl156. Total equivalent gate is 60,508 and maximum frequency is 30Mhz. Our scalar multiplier can be applied to digital signature, encryption and decryption, key exchange, etc. It is applied to a embedded-micom it protects SPA and provides efficient computation.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.20 no.1
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• pp.35-43
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• 1996

A computer program for automatic deriving the symbolic equations of motion for robots using the programming language MATHEMATICA has been developed. The program, developed based on the Lagrange formalism, is applicable to the closed chain robots as well as the open chain robots. The closed chains are virtually cut open, and the kinematics and dynamics of the virtual open chain robot are analyzed. The constraints are applied to the virtually cut joints. As a result, the spatial closed chain robot can be considered as a tree structured open chain robot with kinematic constraints. The topology of tree structured open chain robot is described by a FATHER array. The FATHER array of a link indicates the link that is connected in the direction of base link. The constraints are represented by Lagrange multipliers. The parallel robot, DELTA, having three-dimensional closed chains is modeled and simulated to illustrate the approach.

• Korean Journal of Air-Conditioning and Refrigeration Engineering
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• v.23 no.1
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• pp.87-94
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• 2011

Characteristics of two-phase pressure drop in microchannels were investigated experimentally. The microchannels consisted of 9 parallel trapezoidal channels with each channel having $205\;{\mu}m$ of bottom width, $800\;{\mu}m$ of depth, $3.6^{\circ}$ of sidewall angle, and 7 cm of length. Pressure drops in convective boiling of Refrigerant 113 were measured in the range of inlet pressure 105~195 kPa, mass velocity $150{\sim}920\;kg/m^2s$, and heat flux $10{\sim}100\;kW/m^2$. The total pressure drop generally increased with increasing mass velocity and/or heat flux. Two-phase frictional pressure drop across the microchannels increased rapidly with exit quality and showed bigger gradient at higher mass velocity. A critical review of correlations in the literature suggested that existing correlations were not able to match the experimental results obtained for two-phase pressure drop associated with convective boiling in microchannels. A new correlation suitable for predicting two-phase friction multiplier was developed based on the separated flow model and showed good agreement with the experimental data.

• Journal of Electrical Engineering and Technology
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• v.6 no.6
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• pp.842-848
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• 2011

The current study proposes the design of a hybrid series-parallel resonant converter (SPRC) and a three-stage Cockcroft-Walton voltage multiplier for precisely adjusting the power generated by a continuous wave (CW) $CO_2$ laser. The design of a hybrid SPRC, called LCC resonant converter, is described, and the fundamental approximation of a high-voltage and high-frequency (HVHF) transformer with a resonant tank is discussed. The results of the current study show that the voltage drop and ripple of a three-stage Cockcroft-Walton voltage multiplier depend on frequency. The power generated by a CW $CO_2$ laser can be precisely adjusted by a variable-frequency controller using a DSP (TMS320F2812) microprocessor. The proposed LCC converter could be used to obtain a maximum laser output power of 23 W. Moreover, it could precisely adjust the laser output power within 4.3 to 23 W at an operating frequency range of 187.5 to 370 kHz. The maximum efficiency of the $CO_2$ laser system is approximately 16.5%, and the minimum ripple of output voltage is about 1.62%.

• Journal of KIISE:Computer Systems and Theory
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• v.31 no.1_2
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• pp.112-117
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• 2004

In this paper, we propose a suitable multiplication architecture for cellular automata in a finite field $GF(2^m)$. Proposed least significant bit first multiplier is based on irreducible all one Polynomial, and has a latency of (m+1) and a critical path of $ 1-D_{AND}＋1-D{XOR}$.Specially it is efficient for implementing VLSI architecture and has potential for use as a basic architecture for division, exponentiation and inverses since it is a parallel structure with regularity and modularity. Moreover our architecture can be used as a basic architecture for well-known public-key information service in $GF(2^m)$ such as Diffie-Hellman key exchange protocol, Digital Signature Algorithm and ElGamal cryptosystem.