• Title/Summary/Keyword: parallel labeling

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Parallel Connected Component Labeling Based on the Selective Four Directional Label Search Using CUDA

  • Soh, Young-Sung;Hong, Jung-Woo
    • Journal of the Institute of Convergence Signal Processing
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    • v.16 no.3
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    • pp.83-89
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    • 2015
  • Connected component labeling (CCL) is a mandatory step in image segmentation where objects are extracted and uniquely labeled. CCL is a computationally expensive operation and thus is often done in parallel processing framework to reduce execution time. Various parallel CCL methods have been proposed in the literature. Among them are NSZ label equivalence (NSZ-LE) method, modified 8 directional label selection (M8DLS) method, HYBRID1 method, and HYBRID2 method. Soh et al. showed that HYBRID2 outperforms the others and is the best so far. In this paper we propose a new hybrid parallel CCL algorithm termed as HYBRID3 that combines selective four directional label search (S4DLS) with label backtracking (LB). We show that the average percentage speedup of the proposed over M8DLS is around 60% more than that of HYBRID2 over M8DLS for various kinds of images.

An Improved Hybrid Approach to Parallel Connected Component Labeling using CUDA

  • Soh, Young-Sung;Ashraf, Hadi;Kim, In-Taek
    • Journal of the Institute of Convergence Signal Processing
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    • v.16 no.1
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    • pp.1-8
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    • 2015
  • In many image processing tasks, connected component labeling (CCL) is performed to extract regions of interest. CCL was usually done in a sequential fashion when image resolution was relatively low and there are small number of input channels. As image resolution gets higher up to HD or Full HD and as the number of input channels increases, sequential CCL is too time-consuming to be used in real time applications. To cope with this situation, parallel CCL framework was introduced where multiple cores are utilized simultaneously. Several parallel CCL methods have been proposed in the literature. Among them are NSZ label equivalence (NSZ-LE) method[1], modified 8 directional label selection (M8DLS) method[2], and HYBRID1 method[3]. Soh [3] showed that HYBRID1 outperforms NSZ-LE and M8DLS, and argued that HYBRID1 is by far the best. In this paper we propose an improved hybrid parallel CCL algorithm termed as HYBRID2 that hybridizes M8DLS with label backtracking (LB) and show that it runs around 20% faster than HYBRID1 for various kinds of images.

A Sclable Parallel Labeling Algorithm on Mesh Connected SIMD Computers (메쉬 구조형 SIMD 컴퓨터 상에서 신축적인 병렬 레이블링 알고리즘)

  • 박은진;이갑섭성효경최흥문
    • Proceedings of the IEEK Conference
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    • 1998.10a
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    • pp.731-734
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    • 1998
  • A scalable parallel algorithm is proposed for efficient image component labeling with local operatos on a mesh connected SIMD computer. In contrast to the conventional parallel labeling algorithms, where a single pixel is assigned to each PE, the algorithm presented here is scalable and can assign m$\times$m pixel set to each PE according to the input image size. The assigned pixel set is converted to a single pixel that has representative value, and the amount of the required memory and processing time can be highly reduced. For N$\times$N image, if m$\times$m pixel set is assigned to each PE of P$\times$P mesh, where P=N/m, the time complexity due to the communication of each PE and the computation complexity are reduced to O(PlogP) bit operations and O(P) bit operations, respectively, which is 1/m of each of the conventional method. This method also diminishes the amount of memory in each PE to O(P), and can decrease the number of PE to O(P2) =Θ(N2/m2) as compared to O(N2) of conventional method. Because the proposed parallel labeling algorithm is scalable, we can adapt to the increase of image size without the hardware change of the given mesh connected SIMD computer.

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Study on High Speed Routers(I)-Labeling Algorithms for STC104 (고속라우터에 대한 고찰(I)-STC104의 레이블링 알고리즘)

  • Lee, Hyo-Jong
    • The KIPS Transactions:PartA
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    • v.8A no.2
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    • pp.147-156
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    • 2001
  • A high performance routing switch is an essential device to either the high performance parallel processing or communication networks that handle multimedia transfer systems such as VOD. The high performance routing chip called STC104 is a typical example in the technical aspect which has 32 bidirectional links of 100Mbps transfer sped. It has exploited new technologies, such as wormhole routing, interval labeling, and adaptive routing method. The high speed router has been applied into some parallel processing system as a single chip. However, its performance over the various interconnection networks with multiple routing chips has not been studied. In this paper, the strucrtures and characteristics of the STC104 have been investigated in order to evaluate the high speed router. Various topology of the STC104, such as meshes, torus, and N-cube are defined and constructed. Algorithms of packet transmission have been proposed based on the interval labeling and the group adaptive routing method implemented in the interconnected network. Multicast algorithms, which are often requited to the processor networks and broadcasting systems, modified from U-mesh and U-torus algorithms have also been proposed overcoming the problems of point-to-point communication.

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A Fast and Precise Blob Detection

  • Nguyen, Thanh Binh;Chung, Sun-Tae
    • Proceedings of the Korea Contents Association Conference
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    • 2009.05a
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    • pp.23-29
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    • 2009
  • Blob detection is an essential ingredient process in some computer applications such as intelligent visual surveillance. However, previous blob detection algorithms are still computationally heavy so that supporting real-time multi-channel intelligent visual surveillance in a workstation or even one-channel real-time visual surveillance in a embedded system using them turns out prohibitively difficult. In this paper, we propose a fast and precise blob detection algorithm for visual surveillance. Blob detection in visual surveillance goes through several processing steps: foreground mask extraction, foreground mask correction, and connected component labeling. Foreground mask correction necessary for a precise detection is usually accomplished using morphological operations like opening and closing. Morphological operations are computationally expensive and moreover, they are difficult to run in parallel with connected component labeling routine since they need much different processing from what connected component labeling does. In this paper, we first develop a fast and precise foreground mask correction method utilizing on neighbor pixel checking which is also employed in connected component labeling so that the developed foreground mask correction method can be incorporated into connected component labeling routine. Through experiments, it is verified that our proposed blob detection algorithm based on the foreground mask correction method developed in this paper shows better processing speed and more precise blob detection.

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A Labeling for on-the-fly Detection of Access Anomalies in Nested Parallel Loop Programs with Synchronization Operations (동기화 명령을 가지는 내포 병렬 루프 프로그램의 수행중 접근이상 탐지를 위한 레이블링)

  • 배상현;전용기;배종민
    • Proceedings of the Korean Information Science Society Conference
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    • 1998.10a
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    • pp.712-714
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    • 1998
  • 공유 메모리 병렬 프로그램의 주요 문제의 하나는 공유 변수에 접근하는 비 결정적 수행이다. 본 연구에서는 공유 메모리 병렬 프로그램의 접근이상(access anomaly)을 탐지하는 방법들중 수행중 탐지 기법을 보인다. 수행중 접근이상 탐지기법은 접근이상이 존재하면 적어도 하나는 탐지 할 수 있는 장점을 가지고 있다. 수행중 탐지 기법인 English-Hebrew Labeling 은 동기화 명령을 가지고 내포 병렬 루프 프로그램에서 적용될 수 있는 레이블링 기법으로 레이블링에 많은 저장장소를 필요로 하는 단점을 가지고 있었다. 본 연구에서는 새로운 레이블링 방법을 소개하고, 기존의 English-Hebrew Labeling과 최악의 경우에 기억 장소 복잡도의 측면과 시잔 복잡도의 측면에서 효율성을 비교, 분석하게 된다.

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Real-Time Object Segmentation in Image Sequences (연속 영상 기반 실시간 객체 분할)

  • Kang, Eui-Seon;Yoo, Seung-Hun
    • The KIPS Transactions:PartB
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    • v.18B no.4
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    • pp.173-180
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    • 2011
  • This paper shows an approach for real-time object segmentation on GPU (Graphics Processing Unit) using CUDA (Compute Unified Device Architecture). Recently, many applications that is monitoring system, motion analysis, object tracking or etc require real-time processing. It is not suitable for object segmentation to procedure real-time in CPU. NVIDIA provide CUDA platform for Parallel Processing for General Computation to upgrade limit of Hardware Graphic. In this paper, we use adaptive Gaussian Mixture Background Modeling in the step of object extraction and CCL(Connected Component Labeling) for classification. The speed of GPU and CPU is compared and evaluated with implementation in Core2 Quad processor with 2.4GHz.The GPU version achieved a speedup of 3x-4x over the CPU version.

A Study on the Consumers' Perception and the Improvement for the Use-by-Date of Food (식품 소비기한에 대한 소비자 인식 및 개선에 대한 연구)

  • Park, Mi-Sung;Hong, Yeon-A;Yang, Sung-Bum
    • Korean Journal of Organic Agriculture
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    • v.30 no.3
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    • pp.335-350
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    • 2022
  • The purpose of this study is to help operate and manage the new food period system by investigating consumer perception of sell-by-date and use-by-date, and change of purchasing and consumption period by food period label. Although they have opinions that fit the purpose of introducing the system, such as the need to introduce a use by date, extending the food intake period, and reducing food waste, they still lack an accurate understanding of the system, so education or publicity is needed. In addition, no matter what form of use by date is introduced, products with food expiration date are still likely to be returned or discarded. Therefore, it is desirable to adjust the setting criteria or safety factor for each deadline rather than changing the food period labeling method. In order to reduce consumer confusion and food waste, it is judged that the parallel marking of the sell by date and use by date is appropriate.

A Labeling Scheme for Efficient On-the-fly Detection of Race Conditions in Parallel Programs (병렬프로그램의 경합조건을 수행 중에 효율적으로 탐지하기 위한 레이블링 기법)

  • Park, So-Hee;Woo, Jong-Jung;Bae, Jong-Min;Jun, Yong-Kee
    • The KIPS Transactions:PartA
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    • v.9A no.4
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    • pp.525-534
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    • 2002
  • Race conditions, races in short, need to be detected for debugging parallel programs, because the races result in unintended non-deterministic executions. To detect the races in an execution of program, previous techniques use a centralized data structure which may incur serious bottleneck in generating concurrency information, or show inefficient time complexity which depends on the degree of nested parallelism in comparing any two of them. We propose a new labeling scheme in this paper, which is scalable in generating the concurrency information without bottleneck by using private data structure, and improves time complexity into constant in checking concurrency. The scalability and time efficiency therfore makes on-the-fly race detection efficient not only for programs with either shared-memory or message-passing, but also for programs with mixed model of the two.

Check of Concurrency in Parallel Programs using Image Information (영상정보를 이용한 병렬 프로그램내의 병행성 판별)

  • Park, Myeong-Chul;Ha, Seok-Wun
    • Journal of the Korea Institute of Information and Communication Engineering
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    • v.10 no.12
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    • pp.2132-2139
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    • 2006
  • A parallel program including a nested parallelism has a complex execution aspects and tasks are executed concurrently. This concurrency is a main cause raising most of errors. In this paper, a new method for checking concurrency between two tasks is proposed. The existing techniques for checking the concurrency have their limits to represent a global structure. A new labeling technique that appropriate for image visualization is proposed. To show the global structure by imaging of execution aspects through region partition on 2D plane. On the basis of it, each of the tasks that can distinguish the ordered relation create an independent image. Image information generated by the result simplifies semantic analysis of the related task, and provides an outline of a global execution aspects structure of the program to user effectively.