• 전자공학회논문지B
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• 제30B권5호
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• pp.120-128
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• 1993

In this paper, an implementation of high-speed parallel processing system for neural network design on the multicomputer network is presented. Linear speedup expandability is increased by reducing the synchronization penalty and the communication overhead. Also, we presented the parallel processing models and their performance evaluation models for each of the parallization methods of the neural network. The results of the experiments for the character recognition of the neural network bases on the proposed system show that the proposed approach has the higher linear speedup expandability than the other systems. The proposed parallel processing models and the performance evaluation models could be used effectively for the design and the performance estimation of the neural network on the multicomputer network.

• 대한전기학회논문지:전기물성ㆍ응용부문C
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• 제53권11호
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• pp.577-582
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• 2004

In this paper, lumped equivalent circuits for a conventional parallel directional coupler are proposed. This equivalent circuits only have self inductance and self capacitance, so we can design exact lumped equivalent circuit. The equivalent circuit and design formula for the presented lumped element coupler is derived based on the even- and odd-mode properties of parallel-coupled line. By using the derived design formula, we have designed the 3dB and 4.7dB MMIC couplers at the center frequency of 3.4GHz and 5.6GHz respectively. Measurements for the designed MMIC directional couplers show at 4dB and 5.2dB-coupling value at the center frequency of 3.4GHz and 5.6GHz. Excellent agreements between simulation results and measurement results on the designed directional couplers show the validity of this paper

• 대한전자공학회:학술대회논문집
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• 대한전자공학회 2008년도 하계종합학술대회
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• pp.409-410
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• 2008

This paper presents nonlinear and parallel design for synchronous pipelining in IP-based H.264 decoder implementation. Since H.264 decoder includes the dataflow of feedback loop, the data dependency requires one NOP stage per pipelining latency to drop the throughput into 1/2. Further, it is found that, in execution time, the stage scheduled for MC is more occupied than that for CAVLD/ITQ/DF. The less efficient stage would be improved by nonlinear scheduling, while the fully-utilized stage could be accelerated by parallel scheduling of IP. The optimization yields 3 nonlinear {CAVLD&ITQ}|3 parallel (MC/IP&Rec.)| 3 nonlinear {DF} pipelined architecture for IP-based H.264 decoder. In experiments, the nonlinear and parallel pipelined H.264 decoder, including existing IPs, could deal with full HD video at 41.86MHz, in real time processing.

• 한국정보처리학회논문지
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• 제4권11호
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• pp.2903-2913
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• 1997

본 논문은 공유 및 분산 메모리 구조를 가진 병렬 컴퓨터의 프로그래밍 환경을 지원하기 위하여 ParaC 언어를 설계하고 구현한 내용을 기술한다. ParaC 언어는 확장성 높은 병렬 컴퓨터의 시스템 자원을 사용자가 효과적으로 이용할 수 있도록 설계되었다. 이것은 C 언어에 공유 메모리 환경을 위한 병렬 구문과 동기화 구문, 그리고 분산 메모리 환경을 위한 원격 태스크 구문을 추가함으로써 이루어졌다. 언어의 구현을 위하여 C 언어로의 번역 방법을 기술하였으며, 이 방법을 사용한 번역기와 확장 구문을 위한 실행시간 라이브러리를 구현하였다.

• Journal of the Korean Statistical Society
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• 제13권2호
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• pp.114-120
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• 1984

A parallel flats fraction for the $3^n$ design is defined as union of flats ${t}At=c_i(mod 3)}, i=1,2,\cdots, f$ and is symbolically written as At=C where A is rank r. The A matrix partitions the effects into n+1 alias sets where $u=(3^{n-r}-1)/2. For each alias set the f flats produce an ACPM from which a detection matrix is constructed. The set of all possible parallel flats fraction C can be partitioned into equivalence classes. In this paper, we develop some properties of a detection matrix and C.

• 제어로봇시스템학회:학술대회논문집
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• 제어로봇시스템학회 2000년도 제15차 학술회의논문집
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• pp.429-429
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• 2000

Micro positioning mechanism is the key technology in many fields, such as scanning electron microscopy (SEM), x-ray lithography, mask alignment and micro-machining. In the paper, a 3DOF parallel-type micro-positioning mechanism is proposed. This mechanism uses piezo-actuators and Flexure hinge to control x, y and $\theta$ motion. It is shown both analytically and numerically that 2 DOF flexure hinge model was better precision than 1 DOF flexure hinge design.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 1993년도 추계학술발표회논문집
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• pp.71-75
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• 1993

The Modeling analysis and design of a high frequency LC-type series and LLCC-type parallel resonant converter oprating in the continous conduction is presented. The state-plane diagram representation of the converter response gives and good insight into the converter operation. A set of characterisric frequency are plotted which design parameters can be obtained.

• 대한전기학회:학술대회논문집
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• 대한전기학회 2001년도 하계학술대회 논문집 D
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• pp.2249-2251
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• 2001

This paper proposes that it minimizes interference between link at high speed trajectory tracking of 2-degree parallel link manipulator and QFT(Quantitative Feedback Theory) controller which robust structure uncertainty and disturbance of plant. And using ICD(Individual Channel Design), it separates two channel from multivariable system, parallel link manipulator and designs robust controller with applying MISO QFT to each channel. Finally, we make sure of robustness and excellence of QFT controller through simulation and experiment.

• 한국조명전기설비학회:학술대회논문집
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• 한국조명전기설비학회 2002년도 학술대회논문집
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• pp.157-163
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• 2002

Consideration for parallel operation in a high power system has been increased due to the advantages of parallel operation like as high productivity, simplicity of design, and redundancy of power. This paper discussed the parallel operation of DC-DC Converter, Which Can be used as a high power system, is studied. Based on the small signal model of DC-DC Converter, the simple and exact power stage model of parallel operation system is derived and the parallel operation system using current balance method for the uniform current distribution among the parallel operation system is discussed. To verify the high performance of the proposed DC-DC converter system for parallel operation, the simulation test of the parallel operation, which has 2 Converter modules, is accomplished.

• 전자공학회논문지
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• 제51권2호
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• pp.76-84
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• 2014

최근 고화질 영상의 증가와 더불어 대용량 영상 데이터의 처리는 높은 연산이 요구되어 병렬 처리 설계가 선택되고 있다. 영상 처리에서 나타나는 많은 단순 연산이 병렬처리 가능한 경우, CPU 기반 병렬처리보다는 GPU 기반 병렬처리를 적용하는 것이 계산문제의 시간과 공간 계산 복잡도를 줄일 수 있다. 본 논문은 영상에서 샷 경계 탐지 알고리즘의 병렬 설계와 구현을 연구하였다. 제안하는 샷 경계 탐지 알고리즘은 프레임 간 지역 화소 밝기 비교와 전역 히스토그램 정보를 이용하는데, 이들 데이터의 계산은 대량의 데이터에 대한 높은 병렬성을 갖는다. 이들 연산의 병렬처리를 최대화하기 위해 화소 밝기와 히스토그램의 계산을 NVIDIA GPU에서 병렬 설계 하였다. GPU 기반 샷 탐지 방법은 국가기록원에서 선택된 10개의 비디오 데이터에 대한 성능 테스트를 수행하였다. 테스트에서 GPU 기반 알고리즘의 탐지율은 CPU 기반 알고리즘과 유사하였으나 약 10배의 연산 속도가 개선되었다.