• Proceedings of the KIEE Conference
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• 2001.10a
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• pp.157-160
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• 2001

Recently, with the advancement of internet network the system has been needed to be controllable and observable through internet at industrial workplace. In this study, we developed the digital timer which has a communication function to control and observe many kinds of devices by combining relay and timer used for each type of control panel to realize control solution based on internet to be easily applicable at workplace with low cost and adding 485 serial communication module to have parallel expansibility and safety. And, this system was experimented and designed for easy system management and status check from remote station through internet, appling the developed digital timer to parallel sequence control of motor. As the result of experiment, the circuit configuration would be more simplified than the existing, and it is expected that multi-connection control and monitoring can be simply implemented with low cost equipment at industrial workplace.

• International Journal of Internet, Broadcasting and Communication
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• v.15 no.4
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• pp.270-278
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• 2023

We propose a container orchestration system for process workloads that combines the potential of big data and machine learning technologies to integrate enterprise process-centric workloads. This proposed system analyzes big data generated from industrial automation to identify hidden patterns and build a machine learning prediction model. For each machine learning case, training data is loaded into a data store and preprocessed for model training. In the next step, you can use the training data to select and apply an appropriate model. Then evaluate the model using the following test data: This step is called model construction and can be performed in a deployment framework. Additionally, a visual hierarchy is constructed to display prediction results and facilitate big data analysis. In order to implement parallel computing of PCA in the proposed system, several virtual systems were implemented to build the cluster required for the big data cluster. The implementation for evaluation and analysis built the necessary clusters by creating multiple virtual machines in a big data cluster to implement parallel computation of PCA. The proposed system is modeled as layers of individual components that can be connected together. The advantage of a system is that components can be added, replaced, or reused without affecting the rest of the system.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.24 no.2
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• pp.205-211
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• 2024

The purpose of this study is to implement an agent that intelligently performs tracking and movement through reinforcement learning using the Unity and ML-Agents. In this study, we conducted an experiment to compare the learning performance between training one agent in a single learning simulation environment and parallel training of several agents simultaneously in a multi-learning simulation environment. From the experimental results, we could be confirmed that the parallel training method is about 4.9 times faster than the single training method in terms of learning speed, and more stable and effective learning occurs in terms of learning stability.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.15 no.3
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• pp.146-154
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• 2016

Visible light communication using LED is a technique for transmitting digital data using the light of the LED. Recently, high-speed data rate plays an important role. Therefore, many scholars have researched the MIMO-VLC which is able to increase data rate using a lot of LED transmitters. However, it has problems such as light interference and flicker when transmitting different bit. Many researcher have focused on reduce interference. However it is not considered about flicker problem. Flicker is defined unstable brightness. It occurred the tired of human eyes, lowers eyesight and also decreases concentration. In order to solve this flicker problem in MIMO-VLC, we propose the PFM(Parallel Flicker Mitigation) code. PFM code using combinatorial theory can maintain constant brightness the whole bit duration. Therefore, it is possible to assure the brightness by confirm simulation results.

• The Journal of the Korea institute of electronic communication sciences
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• v.9 no.7
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• pp.791-797
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• 2014

In order to create an environment for Apache Hadoop for parallel distributed processing system of Bigdata, by connecting a plurality of computers, or to configure the node, using the configuration of the virtual nodes on a single computer it is necessary to build a cloud fading environment. However, be constructed in practice for education in these systems, there are many constraints in terms of cost and complex system configuration. Therefore, it is possible to be used as training for educational institutions and beginners in the field of Bigdata processing, development of learning systems and inexpensive practical is urgent. Based on the Raspberry Pi board, training and analysis of Big data processing, such as Hadoop and NoSQL is now the design and implementation of a learning system of parallel distributed processing of possible Bigdata in this study. It is expected that Bigdata parallel distributed processing system that has been implemented, and be a useful system for beginners who want to start a Bigdata and education.

• Journal of Electrical Engineering and Technology
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• v.13 no.6
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• pp.2479-2484
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• 2018

The filter bank multicarrier modulation (FBMC) technique is one of multicarrier modulation technique (MCM), which is mainly used to improve channel capacity of cognitive radio (CR) network and frequency spectrum access technique. The existing FBMC System contains serial to parallel converter, normal QAM modulation, Radix2 inverse FFT, parallel to serial converter and poly phase filter. It needs high area, delay and power consumption. To further reduce the area, delay and power of FBMC structure, a new clock gating technique is applied in the QAM modulation, radix2 multipath delay commutator (R2MDC) based inverse FFT and unified addition and subtraction (UAS) based FIR filter with parallel asynchronous self time adder (PASTA). The clock gating technique is mainly used to reduce the unwanted clock switching activity. The clock gating is nothing but clock signal of flip-flops is controlled by gate (i.e.) AND gate. Hence speed is high and power consumption is low. The comparison between existing QAM and proposed QAM with clock gating technique is carried out to analyze the results. Conversely, the proposed inverse R2MDC FFT with clock gating technique is compared with the existing radix2 inverse FFT. Also the comparison between existing poly phase filter and proposed UAS based FIR filter with PASTA adder is carried out to analyze the performance, area and power consumption individually. The proposed FBMC with clock gating technique offers low power and high speed than the existing FBMC structures.

• Journal of Digital Convergence
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• v.12 no.6
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• pp.231-236
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• 2014

In this paper, we propose a processing speed improvement by adding a parallel processing based on device(graphic card) into a road region extraction by host(PC) based serial processing. The OpenCV CUDA supports the many functions of parallel processing method by interworking a conventional OpenCV with CUDA. Also, when interworking the OpenCV and CUDA, OpenCV functions completed a configuration are optimized the User's device(Graphic Card) specifications. Thus, OpenCV CUDA usage provides an algorithm verification and easiness of simulation result deduction. The proposed method is verified that the proposed method has a about 3.09 times faster processing speed than a conventional method by using OpenCV CUDA and graphic card of NVIDIA GeForce GTX 560 Ti model through experimentation.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.43 no.10 s.352
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• pp.45-53
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• 2006

In this paper, we proposed a parallel hardware architecture for deblocking filter in K264/AVC. The deblocking filter has high efficiency in H.264/AVC, but it also has high computational complexity. For real time video processing, we chose a two 1-D parallel filter architecture, and tried to reduce memory access using dual-port SRAM. The proposed architecture has been described in Verilog-HDL and synthesized on Hynix 0.25um CMOS Cell Library using Synopsys Design Compiler. The hardware size was about 27.3K logic gates (without On-chip Memory) and the maximum operating frequency was 100Mhz. It consumes 258 clocks to process one macroblock, witch means it can process 47.8 HD1080P(1920pixel* 1080pixel) frames per second. It seems that it can be used for real time H.264/AVC encoding and decoding of various multimedia applications.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.16 no.5
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• pp.1-6
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• 2016

Image rotation is one of main pre-processing step in image processing or image pattern recognition. It is implemented with rotation matrix multiplication. However it requires lots of floating point arithmetic operations and trigonometric function calculations, so it takes long execution time. We propose a new high speed image rotation algorithm without two major time-consuming operations. It use just 2 shear translation operations, so it is very fast. In addition, we apply a parallel computing technique with CUDA. CUDA is a massively parallel computing architecture using prevailed GPU recently. As GPU is a dedicated graphic processor, it is exellent for parallel processing of pixels. We compare the proposed algorithm with the conventional rotation one with various size images. Experimental results show that the proposed algorithm is superior to the conventional rotation ones.

• The Journal of The Korea Institute of Intelligent Transport Systems
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• v.9 no.6
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• pp.105-112
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• 2010

Recently, wireless communication systems have been developed and the circuits which operate with the broad-band for multiband uses were introduced. However, broad-band circuits have problems that inevitably increase the size. Dual-band circuit operates only two frequency, therefore, it will be able to miniaturize through unnecessary decreased elements. The Wilkinson power divider is the one of the most commonly used components in wireless communication system for power division. Nowaday, the Wilkinson power divider is also demanded dual-band. In this paper, I propose miniaturized dual-band Wilkinson power divider operating at 2.45 GHz and 5.2 GHz for IEEE 802.11n standard. Proposed dual-band Wilkinson power divider is used in parallel stub line. The design is accomplished by transforming the electrical length and impedance of the quarter wave sections of the conventional Wilkinson power divider into dual band ${\pi}$-shaped sections.