• Journal of Distribution Science
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• v.9 no.2
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• pp.13-24
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• 2011

With the increasing market share of retailer brands, many authors have paid considerable attention to retailer brands. Before market liberalisation in 1996 in Korea, retailer brand market was led by the supermarket retailing format, although the first retailer brand product was developed by the department store format. In parallel with the entry of foreign multiple retailers, the retailer brand market has experienced rapid growth. Particularly, the expansion of Tesco UK with well-established retailing know-how into Korea has encouraged Tesco Korea to actively get involved in retailer brand program. As a result, Tesco Korea has led retailer brand market in the Korean marketplace. The research starts with the question of why Tesco Korea has achieved such a higher retailer brand share. Accordingly, this study is to explore how Tesco UK has transferred its own retailing knowledge into Tesco Korea, in terms of retailer brand program development. In order to explore why the retailer brand share of Tesco Korea is higher than that of its counterparts, the author adopted in-depth interview with prepared-questions and store observation as a research methodology. To examine working process as well as information flows within Tesco Korea and from UK to Korea, in-depth interview method is one of the most suitable research methodologies, because of the difficulty of quantifying information or data related to work flows. In addition, to increase the validity of information, the researcher had interviews with Tesco Korea supplier and store personnel. Based on these research techniques, this research explored how Tesco UK has influenced or advised Tesco Korea, particularly, from the point of view of knowledge transfer. Since the entry of Tesco UK into Korea as a joint-venture, the retailer brand market share of Tesco Korea has continuously increased. It would be expected that Tesco UK has helped Tesco Korea to settle down in the Korean market. During interviews with Tesco and a Tesco supplier, the researcher found that Tesco Korea has obviously taken an advantage of retailing know-how created by Tesco UK. Furthermore, the retailer brand development and handling process of Tesco Korea has been operated with the help of Tesco UK. This might mean that Tesco UK has directly or indirectly an impact on the improvement of Korean retailer brand development skills. As a mechanism to transfer retailing knowledge developed in the home market into the host market, one of the international retailers, Tesco UK has adopted many different ways such as annual meeting, trading meeting to import or export own retailer brand products, offering of operation manual developed by Tesco UK and buyer cooperation between Tesco UK and Korea, in order to share information. Through these communication techniques, the knowledge of Tesco UK has been transferred to Tesco Korea. This research accordingly suggests that retailer brand market share is apparently related to how sophisticated or advanced the knowledge of the retailer brand development and handling process of retailers are. It is also demonstrated by this research that advanced development and handling skills make a considerable contribution to increasing retailer brand share in markets with a lower share or no presence of retailer brands.

• The Journal of Society for e-Business Studies
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• v.18 no.4
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• pp.45-65
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• 2013

A design file can get larger in size as the complexity of the target object increases. A large design file may reside in a large parallel computing system, such as cloud computing systems, and many designers may work concurrently on the same design file. In such a case, it is obvious that we need some kind of protection mechanism so that each user can access only the area of the file he or she is entitled to. Two approaches can be taken for this problem: one is the traditional access control mechanisms and the other encryption techniques. We take the latter approach to ensure the safety of the file even in public domain such as clouding systems, and in this paper, we suggest an encryption scheme for a file where the file is encrypted in multi-layer so that each user is allowed to access the file only at the layer for which the user has the proper access right. Each layer of the file is encrypted with different keys and these keys are exposed only to those who have the right access permit. The paper explains the necessary file format to achieve this goal and discusses the file manipulation functions to handle this new file format.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.44 no.8
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• pp.30-37
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• 2007

An exponentiation in $GF(2^m)$ is a basic operation for several algorithms used in cryptography, digital signal processing, error-correction code and so on. Existing hardware implementations for the exponentiation operation organize by Right-to-Left method since a merit of parallel circuit. Our paper proposes a polynomial exponentiation structure with a trinomial that is organized by Left-to-Right method and that utilizes a weakly dual basis. The basic idea of our method is to decrease time delay using precomputation tables because one of two inputs in the Left-to-Right method is fixed. Since $T_{sqr}$ (squarer time delay) + $T_{mul}$(multiplier time delay) of ow method is smaller than $T_{mul}$ of existing methods, our method reduces time delays of existing Left-to-Right and Right-to-Left methods by each 17%, 10% for $x^m+x+1$ (irreducible polynomial), by each 21%, 9% $x^m+x^k+1(1, by each 15%, 1% for $x^m+x^{m/2}+1$.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.1A
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• pp.93-98
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• 2004

Serial ATA interface Is inexpensive comparatively and performance is superior. So it is suitable technology in demand that now require data transmission and throughput of high speed. This paper describes a design and implementation of Serial ATA Link layer about error detection and 8b/10b encoder/decoder for DC balance in frequency 150MHz. The 8b/10b Encoder is partitioned into a 5b/6b plus a 3b/4b coder. The logical model of the block is described by using Verilog HDL at register transistor level and the verified HDL is synthesized using standard cell libraries. And it is fabricated with $0.35{\mu}m$ Standard CMOS Cell library and the chip size is about $1500{\mu}m\;*\;1500{\mu}m$. The function of this chip has been verified and tested using testboard with FPGA equipment and IDEC ATS2 test equipment. It is used to frequency of 100MHz in verification processes and supply voltage 3.3V. The result of testing is well on the system clock 100MHz. The designed and verified each blocks may be used IP in the field of high speed serial data communication.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.21 no.12
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• pp.3235-3245
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• 1996

A DDFS(Direct Digital Frequency Synthesizer) used in spread spectrum communication systems must need fast switching speed, high resolution(the step size of the synthesizer), small size and low power. The chip has been designed with four parallel sine look-up table to achieve four times throughput of a single DDFS. To achieve a high processing speed DDFS chip, a 24-bit pipelined CMOS technique has been applied to the phase accumulator design. To reduce the size of the ROM, each sine ROM of the DDFS is stored 0-.pi./2 sine wave data by taking advantage of the fact that only one quadrant of the sine needs to be stored, since the sine the sine has symmetric property. And the 8 bit of phase accumulator's output are used as ROM addresses, and the 2 MSBs control the quadrants to synthesis the sine wave. To compensate the spectrum purity ty phase truncation, the DDFS use a noise shaper that structure like a phase accumlator. The system input clock is divided clock, 1/2*clock, and 1/4*clock. and the system use a low frequency(1/4*clock) except MUX block, so reduce the power consumption. A 107MHz DDFS(Direct Digital Frequency Synthesizer) implemented using 0.8.mu.m CMOS gate array technologies is presented. The synthesizer covers a bandwidth from DC to 26.5MHz in steps of 1.48Hz with a switching speed of 0.5.mu.s and a turing latency of 55 clock cycles. The DDFS synthesizes 10 bit sine waveforms with a spectral purity of -65dBc. Power consumption is 276.5mW at 40MHz and 5V.

• Journal of the Institute of Electronics and Information Engineers
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• v.50 no.3
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• pp.59-67
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• 2013

Reed-Solomon (RS) codes are powerful error-correcting codes used in diverse applications. Recently, algebraic soft-decision decoding algorithm for RS codes that can correct the errors beyond the error correcting bound has been proposed. The algorithm requires very intensive computations for interpolation, therefore an efficient VLSI architecture, which is realizable in hardware with a moderate hardware complexity, is mandatory for various applications. In this paper, we propose an efficient architecture with low hardware complexity for interpolation in soft-decision list decoding of Reed-Solomon codes. The proposed architecture processes the candidate polynomial in such a way that the terms of X degrees are processed in serial and the terms of Y degrees are processed in parallel. The processing order of candidate polynomials adaptively changes to increase the efficiency of memory access for coefficients; this minimizes the internal registers and the number of memory accesses and simplifies the memory structure by combining and storing data in memory. Also, the proposed architecture shows high hardware efficiency, since each module is balanced in terms of latency and the modules are maximally overlapped in schedule. The proposed interpolation architecture for the (255, 239) RS list decoder is designed and synthesized using the DongbuHitek $0.18{\mu}m$ standard cell library, the number of gate counts is 25.1K and the maximum operating frequency is 200 MHz.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.15 no.5
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• pp.486-492
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• 2004

In this paper, we newly propose the binary CA-CDMA(constant amplitude CDMA) system using pre-coding method to solve the high PAPR problem caused by multi-user signal transmission in the CDMA system. 4-user CA-CDMA, the basis of proposed binary CA-CDMA system, makes binary output signal for 4 input users. It produces the output of binary(${\pm}$2) amplitude by using a parity signal resulting from the XOR operation of 4 users data. Another sub-channel or more bandwidth is not necessary because it is transmitted together with user data and can be easily recovered in the receiver. The extension of the number of users can be possible by the simple repetition of the basic binary 4-user CA-CDMA. For example, binary 16-user CA-CDMA is made easily by allocating the four 4-user CA-CDMA systems in parallel and leading the four outputs to the fifth 4-user CA-CDMA system as input, because the output signal of each 4-user CA-CDMA is also binary. By the same extension procedure, binary 64 and 256-user CA-CDMA systems can be made with the constant amplitude. As a result, the code rate of this proposed CA-CDMA system is just 1 and binary CA-CDMA does not change the transmission rate with the constant output signal(PAPR = 0 ㏈). Therefore, the power efficiency of the HPA can be maximized without the nonlinear distortion. From the simulation results, it is verified that the conventional CDMA system has multi-level output signal, but the proposed binary CA-CDMA system always produces binary output. And it is also found that the BER of conventional CDMA system is increased by nonlinear HPA, but the BER of proposed binary CA-CDMA system is not changed.

• Journal of Korea Spatial Information System Society
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• v.11 no.3
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• pp.9-18
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• 2009

Recently, due to the advanced technologies of mobile devices and wireless communication, there are many studies on telematics and LBS(location-based service) applications. because moving objects usually move on spatial networks, their locations are updated frequently, leading to the degradation of retrieval performance. To manage the frequent updates of moving objects' locations in an efficient way, a new distributed grid scheme, called DS-GRID (distributed S-GRID), and k-NN(k-nearest neighbor) query processing algorithm was proposed[1]. However, the result of k-NN query processing technique may be invalidated as the location of query and moving objects are changed. Therefore, it is necessary to study on continuous k-NN query processing algorithm. In this paper, we propose both MCE-CKNN and MBP(Monitoring in Border Point)-CKNN algorithmss are S-GRID. The MCE-CKNN algorithm splits a query route into sub-routes based on cell and seproves retrieval performance by processing query in parallel way by. In addition, the MBP-CKNN algorithm stores POIs from the border points of each grid cells and seproves retrieval performance by decreasing the number of accesses to the adjacent cells. Finally, it is shown from the performance analysis that our CKNN algorithms achieves 15-53% better retrieval performance than the Kolahdouzan's algorithm.

• Journal of Korean Society of Industrial and Systems Engineering
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• v.4 no.4
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• pp.43-61
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• 1981

Interest in the Quality of working life is spreading rapidly and the phrase has entered the popular vocabulary. That this should be so is probably due in large measure to changes in the values of society, nowadays accelerated as never before by the concerns and demands of younger people. But however topical the concept has become, there is very little agreement on its definition. Rather, the term appears to have become a kind of depository for a variety of sometimes contradictory meanings attributed to it by different groups. A list of all the elements it if held to cover would include availability and security of employment, adaquate income, safe and pleasant physical working conditions, reasonable hours of work, equitable treatment and democracy in the workplace, the possibility of self-development, control over one's work, a sense of pride in craftsmanship or product, wider career choices, and flexibility in matters such as the time of starting work, the number of working days in the week, Job sharing and so on altogether an array that encompasses a variety of traditional aspirations and many new ones reflecting the entry into the post industrial era. The term "quality of working life" was introduced by professor Louis E. Davis and his colleagues in the late 1960s to call attention to the prevailing and needlessly poor quality of life at the workplace. In their usage it referred to the quality of the relationship between the worker and his working environment as a whole, and was intended to emphasize the human dimension so often forgotten among the technical and economic factors in job design. Treating workers as if they were elements or cogs in the production process is not only an affront to the dignity of human life, but is also a serious underestimation of the human capabilities needed to operate more advanced technologies. When tasks demand high levels of vigilence, technical problem-solving skills, self initiated behavior, and social and communication skills. it is imperative that our concepts of man be of requisite complexity. Our aim is not just to protect the worker's life and health but to give them an informal interest in their job and opportunity to express their views and exercise control over everything that affects their working life. Certainly, so far as his work is concerned, a man must feel better protected but he must also have a greater feeling of freedom and responsibility. Something parallel but wholly different if happening in Europe, industrial democracy. What has happened in Europe has been discrete, fixed, finalized, and legalized. Those developing centuries driving toward industrialization like R.O.K, shall have to bear in mind the human complexity in processing and designing the work and its environment. Increasing attention is needed to the contradiction between autocratic rule at the workplace and democratic rights in society.n society.

• Journal of the Institute of Electronics and Information Engineers
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• v.49 no.10
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• pp.217-230
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• 2012

This paper propose interacting test programming methods between test equipment and hardware unit to verify function and performance of the hardware unit under test. Proposed test program can minimizes the risk of failures when the unit is mounted on the aircraft by testing and verifying the unit under the worst stress condition. Also, Object oriented design using UML make it easy to apply in other equipments. Test program consists of architecture package and hardware package. Architecture package is in a role for system management, log analysis, message receiving and message analysis. Messages that are used by system management define messages for testing and defined messages is sent and received to test equipment through Ethernet. Hardware package is in a role for hardware management that is needed to be tested and is related to a system. Hardware to be tested is divided into internal test and transmission test. Internal test inspects hardware itself and reports the test results to the test equipment. Transmission test inspects communication device by sending or receiving data. All kinds of test is done in the worst condition of the test unit executing in parallel. Each device is tested at least 482 times and at most 15,003 times about one hour. Test program is utilized in hardware reliability test like as environmental test or EMI test.