• Journal of Information Processing Systems
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• v.7 no.2
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• pp.271-286
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• 2011

In this paper, we propose efficient algorithms for parallel prefix computation and sorting on a recursive dual-net. The recursive dual-net $RDN^k$(B) for k > 0 has $(2n_o)^{2K}/2$ nodes and $d_0$ + k links per node, where $n_0$ and $d_0$ are the number of nod es and the node-degree of the base-network B, respectively. Assume that each node holds one data item, the communication and computation time complexities of the algorithm for parallel prefix computation on $RDN^k$(B), k > 0, are $2^{k+1}-2+2^kT_{comm}(0)$ and $2^{k+1}-2+2^kT_{comp}(0)$, respectively, where $T_{comm}(0)$ and $T_{comp}(0)$ are the communication and computation time complexities of the algorithm for parallel prefix computation on the base-network B, respectively. The algorithm for parallel sorting on $RDN^k$(B) is restricted on B = $Q_m$ where $Q_m$ is an m-cube. Assume that each node holds a single data item, the sorting algorithm runs in $O((m2^k)^2)$ computation steps and $O((km2^k)^2)$ communication steps, respectively.

• Journal of the Institute of Convergence Signal Processing
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• v.5 no.3
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• pp.236-242
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• 2004

In this paper, we propose an approach to parallelize a load balancing algorithm that was shown to be very effective in distributing workload for parallel computations. Load balancing algorithms are required in executing parallel program efficiently As a parallel computation model, we used dynamically growing tree structure that can be found in many application problems. The load balancing algorithm tries to balance the workload among processors while keeping the communication cost under certain limit. We show how the load balancing algorithm is effectively parallelized on mesh and hypercube interconnection networks, and analyzed the time complexity for each case to show that parallel algorithm actually reduced the various overhead.

• The Transactions of The Korean Institute of Electrical Engineers
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• v.66 no.1
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• pp.100-106
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• 2017

In this paper, we propose a parallel optimization method of Aho-Corasick (AC) algorithm and Parallel Failureless Aho-Corasick (PFAC) algorithm using Open Computing Language (OpenCL) on Field Programmable Gate Array (FPGA). The low throughput of string matching engine causes the performance degradation of network process. Recently, many researchers have studied the string matching engine using parallel computing. FPGA's vendors offer a parallel computing platform using OpenCL. In this paper, we apply the AC and PFAC algorithm on DE1-SoC board with Cyclone V FPGA, where the optimization that considers FPGA architecture is performed. Experiments are performed considering global id, local id, local memory, and loop unrolling optimizations using PFAC algorithm. The performance improvement using loop unrolling is 129 times greater than AC algorithm that not adopt loop unrolling. The performance improvements using loop unrolling are 1.1, 0.2, and 1.5 times greater than those using global id, local id, and local memory optimizations mentioned above.

• Journal of applied mathematics & informatics
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• v.11 no.1_2
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• pp.201-213
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• 2003

In this paper we present a second order PVT (parallel variable transformation) algorithm converging to second order stationary points for minimizing smooth functions, based on the first order PVT algorithm due to Fukushima (1998). The corresponding stopping criterion, descent condition and descent step for the second order PVT algorithm are given.

• Proceedings of the KIEE Conference
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• 2001.07e
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• pp.134-140
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• 2001

Parallel processing has the potential to be cost effectively used on computationally intense power system problems. But this technology is not still available is not only parallel computer but also parallel processing scheme. Testing these algorithms to ensure accuracy, and evaluation of their performance is also an issue. Although a significant amount of parallel algorithms of power system problem have been developed in last decade, actual testing on processor architectures lies in the beginning stages. This paper presents the parallel processing algorithm to supply the base being able to treat power flow by newton's method by the distributed memory type parallel computer. This method is to assign and to compute teared blocks of sparse matrix at each parallel processors. The testing to insure accuracy of developed method have been done on serial computer by trying to simulate a parallel environment.

• Journal of Korea Multimedia Society
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• v.1 no.2
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• pp.154-161
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• 1998

This paper proposes a parallel processor system which processes cultural assets image recognition and retrieval algorithm in real time. A serial algorithm which is developed for the parallel processor system is parallellized. The parallel processor system consists of a control unit, 100 PE(Processing Elements), and 10 Park's multi-access memory systems which has 11 memory modules per each one. The parallel processor system is simulated by CADENCE Verilog-XL which is a package for the hardware simulation. With the same simulated results as that of the serial algorithm, the speed ratio of the parallel algorithm to the serial one is 81. The parallel processor system we proposed is quite effective for cultural assets image processing.

• KIPS Transactions on Software and Data Engineering
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• v.12 no.5
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• pp.207-216
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• 2023

For decoding-compatible parallel Deflate algorithm, this study proposed a new method of the control header being made in such a way that essential information for parallel compression and decompression are stored in the Disposed Bit Area (DBA) of the non-compression block and being inserted into the compressed blocks. Through this, parallel compression and decompression are possible while maintaining perfect compatibility with the existing decoder. After applying this method, the compression time was reduced by up to 71.2% compared to the sequential processing method, and the parallel decompression time was reduced by up to 65.7%. In particular, it is well known that parallel decompression is impossible due to the structural limitations of the Deflate algorithm. However, the decoder equipped with the proposed method enables high-speed parallel decompression at the algorithm level and maintains compatibility, so that parallelly compressed data can be decoded normally by existing decoder programs.

• Proceedings of the IEEK Conference
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• 2003.07c
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• pp.2561-2564
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• 2003

Data mining is an effective method of the discovery of useful information such as rules and previously unknown patterns existing in large databases. The discovery of association rules is an important data mining problem. We have developed a new parallel mining called Distributed Frequent Pattern Tree (abbreviated by DFPT) algorithm on a distributed shared nothing parallel system to detect association rules. DFPT algorithm is devised for parallel execution of the FP-growth algorithm. It needs only two full disk data scanning of the database by eliminating the need for generating the candidate items. We have achieved good workload balancing throughout the mining process by distributing the work equally to all processors. We implemented the algorithm on a PC cluster system, and observed that the algorithm outperformed the Improved Count Distribution scheme.

• Proceedings of the KIPE Conference
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• 2016.07a
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• pp.479-480
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• 2016

This paper introduces a master and slave control algorithm for parallel operation of UPS system. If each module of UPS system control the output voltage and filter inductor current in parallel operation, it occur unbalanced output power each module. To operate UPS system parallel, it need a algorithm that control output power of modules. A master and slave control algorithm is helpful to balance output power of modules by controlling output current. The effect of a master and slave control algorithm is proved by simulations.

• Journal of Korea Multimedia Society
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• v.18 no.10
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• pp.1180-1188
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• 2015

In this paper, a parallel cell contour line extraction algorithm using CUDA, which has no inner contour lines, is proposed. The contour of a cell is very important in a cell image analysis. It could be obtained by a conventional serial contour tracing algorithm or parallel morphology operation. However, the cell image has various damages in acquisition or dyeing process. They could be turn into several inner contours, which make a cell image analysis difficult. The proposed algorithm introduces a min-max coordinates table into each CUDA thread block, and removes the inner contour in parallel. It is 4.1 to 7.6 times faster than a conventional serial contour tracing algorithm.