• The Journal of Korean Institute of Communications and Information Sciences
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• v.27 no.4A
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• pp.301-309
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• 2002

In this paper, we propose the effective implementation of various nonlinear combiners using by PS-LFSR: m-parallel memoryless-nonlinear combiner, m-parallel memory-nonlinear combiner, m-parallel nonlinear filter function, and m-parallel clock-controlled function. Finally, we propose m-parallel LILI-128 stream cipher as an example of the parallel implementation, and we determine its cryptographic security and performance.

• The Pure and Applied Mathematics
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• v.14 no.3
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• pp.161-166
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• 2007

Given operators X and Y acting on a Hilbert space H, an interpolating operator is a bounded operator A such that AX = Y. An interpolating operator for n-operators satisfies the equation $AX_i=Y_i$, for i = 1,2,...,n. In this article, we showed the following: Let L, be a subspace lattice on a Hilbert space H and let X and Y be operators in B(H). Then the following are equivalent: (1) $$sup\{\frac{{\parallel}E^{\bot}Yf{\parallel}}{{\overline}{\parallel}E^{\bot}Xf{\parallel}}\;:\;f{\epsilon}H,\;E{\epsilon}L}\}\;<\;{\infty},\;sup\{\frac{{\parallel}Xf{\parallel}}{{\overline}{\parallel}Yf{\parallel}}\;:\;f{\epsilon}H\}\;<\;{\infty}$$ and $\bar{range\;X}=H=\bar{range\;Y}$. (2) There exists an invertible operator A in AlgL such that AX=Y.

• The Transactions of the Korean Institute of Electrical Engineers B
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• v.52 no.4
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• pp.154-160
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• 2003

The switched reluctance motor(SRM) has a considerable potential for industrial applications because of its high reliability as a result of the absence of rotor windings. In some applications with SRM, a parallel switching strategy is often used for cost saving, increasing of current capacity and system reliability. This paper proposes a new parallel switching strategy of SRM using parallel winding. While conventional parallel switching devices are connected in a phase winding, power devices are connected in the parallel windings wound in each pole of stator in the proposed method. Paralleling strategy for current sharing in the proposed method can be easily determined without considerations of any nonlinear characteristics of power devices such as conduction resistance, threshold voltage and gain factor. The proposed paralleling strategy is verified by the mathematical analysis and experimental results.

• The Transactions of the Korean Institute of Electrical Engineers A
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• v.52 no.4
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• pp.154-154
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• 2003

The switched reluctance motor(SRM) has a considerable potential for industrial applications because of its high reliability as a result of the absence of rotor windings. In some applications with SRM, a parallel switching strategy is often used for cost saving, increasing of current capacity and system reliability. This paper proposes a new parallel switching strategy of SRM using parallel winding. While conventional parallel switching devices are connected in a phase winding, power devices are connected in the parallel windings wound in each pole of stator in the proposed method. Paralleling strategy for current sharing in the proposed method can be easily determined without considerations of any nonlinear characteristics of power devices such as conduction resistance, threshold voltage and gain factor. The proposed paralleling strategy is verified by the mathematical analysis and experimental results.

• The Pure and Applied Mathematics
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• v.23 no.2
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• pp.155-162
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• 2016

In this paper, we solve the additive ρ-functional inequalities (0.1)${\parallel}f(x+y)+f(x-y)-2f(x){\parallel}$ $\leq$ ${\parallel}{\rho}(2f(\frac{x+y}{2})+f(x-y)-2f(x)){\parallel}$, where ρ is a fixed complex number with |ρ| < 1, and (0.2) ${\parallel}2f(\frac{x+y}{2})+f(x-y)-2f(x)){\parallel}$ $\leq$ ${\parallel}{\rho}f(x+y)+f(x-y)-2f(x){\parallel}$, where ρ is a fixed complex number with |ρ| < 1. Furthermore, we prove the Hyers-Ulam stability of the additive ρ-functional inequalities (0.1) and (0.2) in complex Banach spaces.

• The Pure and Applied Mathematics
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• v.23 no.2
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• pp.145-153
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• 2016

In this paper, we solve the quadratic ρ-functional inequalities (0.1) ${\parallel}f(x+y)+f(x-y)-2f(x)-2f(y){\parallel}$ $\leq$ ${\parallel}{\rho}(4f(\frac{x+y}{2})+f(x-y)-2f(x)-2f(y)){\parallel}$, where $\rho$ is a fixed complex number with $\left|{\rho}\right|$ < 1, and (0.2) ${\parallel}4f(\frac{x+y}{2})+f(x-y)-2f(x)-2f(y){\parallel}$ $\leq$ ${\parallel}{\rho}(f(x+y)+f(x-y)-2f(x)-2f(y)){\parallel}$, where ρ is a fixed complex number with |ρ| < $\frac{1}{2}$. Furthermore, we prove the Hyers-Ulam stability of the quadratic ρ-functional inequalities (0.1) and (0.2) in complex Banach spaces.

• Journal of the Korea Society for Simulation
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• v.7 no.1
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• pp.69-83
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• 1998

In this paper, we present the results of simulation by running parallel VHDL simulation on typical MPP(Massively Parallel Processor) systems such as IBM SP2 and SGI Origin 2000. Parallel simulation uses the synchronous protocol and parallel program is implemented using MPI(Message Passing Interface) based on message passing model, so that it can urn on any parallel programming environment which supports MPI, a standard communication library. And then GVT(Global Virtual Time) computation for parallel simulation is based on the global broadcasting with MPI＿Bcast(), which is a standard function in MPI and piggybacking. Our benchmark exhibits that as size of VHDL grows, the parallel simulation has a better performance compared with the sequential simulation. In addition, we also show the results of comparison between IBM SP2 and SGI Origin 2000 by applying the same application to those indirectly.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.34 no.10A
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• pp.776-783
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• 2009

Current-cut circuit is an effective method to obtain low power consumption in wireless communication systems as high speed OFDM. For the operation of current-mode FFT LSI with analog signal processing essentially requires current-mode serial-to-parallel/parallel-to-serial converter with multi input and output structure. However, the Hold-mode operation of current-mode serial-to-parallel/parallel-to-serial converter has unnecessary power consumption. We propose a novel current-mode serial-to-parallel/parallel-to-serial converter with current-cut circuit and full chip simulation results agree with experimental data of low power consumption. The proposed current-mode serial-to-parallel/parallel-to-serial converter promise the wide application of the current-mode analog signal processing in the field of low power wireless communication LSI.

• The Transactions of the Korea Information Processing Society
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• v.6 no.2
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• pp.485-496
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• 1999

Comparing with sequential programming, parallel programming has additional complexity due to the consideration of parallelism, communication and synchronization of processes. A synergism between users and compliers should be established, each assisting the other to produce high quality parallel programs. On the above underlying philosophy, we developed a parallel Object-Oriented specification language, POOSL, as preliminary works. However, it is still likely to hard for users to write parallel program because users have to consider grammar of POOSL and to write text-based parallel program. It would be more desirable to provide users wit visual environment for effective parallel programming. Therefore, we propose a visual programming environment. VEPO(Visual environment for Parallel Object-Oriented Programming), based on POOSL in order that users can develop parallel programs more easily and conveniently. It aims at supporting a programming environment in which users can represent their programs more naturally and visually I parallel manner with object-oriented concept and essential steps during parallel program development such as program specification, compilation, execution and animation of execution are integrated. VEPO has useful features for parallel processing. Especially, complicated parallel codes for synchronization and communication of processes are automatically generated in the translation phase, so users can be relieved of writing error-prone parallel codes. The system is targeted to the transputer-based parallel system, MC-3. The graphic user interface of VEPO was implemented using Visual C++. Visual programs descirbed on VEPO are translated into Inmos C and executed on MC-3.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.32 no.10
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• pp.38-45
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• 2004

In this paper, a parallel visualization algorithm is proposed for efficient visualization of the massive data generated from large-scale parallel finite element analysis through investigating the characteristics of parallel rendering methods. The proposed parallel visualization algorithm is designed to be highly compatible with the characteristics of domain-wise computation in parallel finite element analysis by using the sort-last-sparse approach. In the proposed algorithm, the binary tree communication pattern is utilized to reduce the network communication time in image composition routine. Several benchmarking tests are carried out by using the developed in-house software, and the performance of the proposed algorithm is investigated.