• Transactions of Materials Processing
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• v.24 no.2
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• pp.107-114
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• 2015

The current study presents a geometric measurement and analysis of the section profile for a feature line surface on an automotive outer panel. A feature line surface is the geometry which is a visually noticeable creased line on a smooth panel. In the current study the section profile of a feature line surface is analyzed geometrically. The section profile on the real press panel was measured using a coordinate measuring machine. The section profiles from the CAD model and the real panel are aligned using the same coordinate system defined by two holes near the feature line. In the aligned section profiles the chord length and height of the curved part were measured and analyzed. The results show that the feature line surface on the real panel is doubled in width size.

• Journal of the Korean Society of Safety
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• v.27 no.6
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• pp.160-165
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• 2012

The process of panel line in the shipyard produce the panel of outside planking which is located the side and bottom of a ship. The stiffeners or plates are welded onto the plates in this process. In this study, the panel line was performed to work process analysis and was analyzed into the IDEF0(Integration Definition) model that is functional modeling methodology. Also the panel line was analyzed to find out the risk factor and expected accident/safety guide from each process. And then this outputs were applied to the IDEF0 model. The mobile application which is designed by ooCBD(Object-oriented Component Based Development) method is able to use the output data of the process analysis in the panel line. This mobile application could be used by employees and safety managers without regard for working location and time.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.11
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• pp.1019-1023
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• 2005

We have examined the electrical and optical characteristics of the plasma display panel produced by vacuum in-line sealing technology. In the MgO layer deposited at room temperature, after sealing at the panel temperature of $430^{\circ}C$, the luminous efficiency decreased compared with that of the panel before sealing. Moreover, firing and sustain voltage of the sealed panel increased compared with that of the panel before sealing. This was resulted from that the MgO protective layer was cracked by the softening of the dielectric layer during the sealing process. In order to avoid the MgO crack during the vacuum in-line sealing, thermally stable MgO layer or lower temperature sealing is required.

• Proceedings of the Safety Management and Science Conference
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• 2009.04a
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• pp.523-529
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• 2009

The ACF(Anisotropic Conductive Film) is used for bonding Drive IC and OLED display device panel. If ACF bonding process is problem, a malfunction of line defect can occur. Because electric resistance increase between the panel and drive IC after a period of time, drive IC can not supply enough current to the panel. This paper is studied on a method of test for line defect.

• The Transactions of the Korean Institute of Electrical Engineers C
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• v.48 no.12
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• pp.768-772
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• 1999

A new TFT-LCD panel with air-bridge type gate to data line inter-crossing has been proposed and its characteristics have been measured. The proposed structure has air-gap between gate and data line inter-crossing. This air-bridge TFT-LCD panel has very small capacitance between gate and data line. The new panes structure achieves 9 times fast signal propagation compared with conventional panel, which enables to have enough design margin for 20-inch diagonal and larger size UXGA panel. We have examined thermal and mechanical durability of new panel to verify applicability for commercial AMLCD production. After TEOS and polyimide passivation, this panel withstood a thermal stress at $250^{\circ}C$ and a mechanical stress during the rubbing process.

• Proceedings of the IEEK Conference
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• 2003.07e
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• pp.1783-1786
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• 2003

In this paper, an automated line-defect detection method for TFT-LCD panel is presented. A DFB(Directional Filter Bank) and line-projection method are used to find line-defect which is one of the major defects occurred in TFT-LCD panel. The experimental results show that the proposed algorithm gave promising results for applying automated inspection technique for TFT-LCD panel.

• Journal of Korean Ophthalmic Optics Society
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• v.6 no.1
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• pp.139-144
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• 2001

In order to analyze of the color perception Farnsworth Test Panel D-15 in the CIELab color space coordinates, it was measured by the reflectance spectrum of the 380~780nm wavelength regions. The Test Panel D-15 was situated in the near origin point of higher the saturation in CIELab coordinates (a, b). Normal person perceived to the similar color for the color of small color difference, and color deficiency person depended on the confusing color line and the neutral point unconcerned with the color difference. In case of Ptotanopia, Deutrnopia, r-g defect, y-b defect with the color deficiency, the neutral points position (a,b) were each (2.12,1.02), (4.25,2.05), (2.51,0.25), (1.20,-1.10).

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.46 no.9
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• pp.14-24
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• 2009

Memory cell array and peripheral circuits are designed for system on panel style frame buffer. Moreover, a parallel test methodology to test multiple blocks of memory cells is proposed to overcome low yield of system on panel processing technologies. It is capable of faster fault detection compared to conventional memory tests and also applicable to the tests of various embedded memories and conventional SRAMs. The various patterns of conventional test vectors can be used to enhance fault coverage. The proposed testing method is also applicable to hierarchical bit line and divided word line, one of design trends of recent memory architectures.

• Korean Journal of Computational Design and Engineering
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• v.13 no.1
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• pp.36-44
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• 2008

This paper proposes a modeling and simulation process of a panel production line (PPL) in a shipyard. The panel production line is an assembly process to produce a main panel of a flat block and a curved block. In this paper, its activity analysis is carried out using expression of IDEF0, and its process is qualitatively and quantitatively analyzed and modeled by Petri Nets. A commercial discrete event simulation tool, $QUEST^{TM}$, is used for virtual PPL and simulation. The modeling results by Petri Net are mapped to elements of the simulation tool. Finally, an integrated simulation environment of PPL is implemented in order to efficiently utilize the virtual PPL model. With the help of IDEF0 and Petri Nets, we could systematically analyze and describe the PPL process that are characterized as being concurrent, asynchronous, distributed, parallel, nondeterministic, and/or stochastic. Also, the dynamic and concurrent activities of a PPL system were able to be simulated. A timing concept can be included into the Petri nets model to evaluate performance and dependability issues of the system.

• Journal of Advanced Marine Engineering and Technology
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• v.30 no.2
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• pp.304-310
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• 2006

A typical honeycomb sandwich panel consists of two thin, high-strength facings bonded to a thick, light-weight core. Each component by itself is relatively weak and flexible, but when it combined in a sandwich panel they produce a structure that is stiff, strong, and lightweight. To prove the suitability the honeycomb sandwich structure with prepreg, the mechanical properties of the skin materials and honeycomb sandwich structure were evaluated with the static strength tests. Accordingly, the honeycomb sandwich structure made by autoclave process is available for a panel on LCD/PDP assembly line.