• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2001.07a
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• pp.119-126
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• 2001

Chip-on-glass(COG) mounting of area array electronic packages was attempted by heating the rear surface of a contact pad film deposited on a glass substrate. The pads consisted of an adhesion(i.e. Cr or Ti) and a top coating layer(i.e. Ni or Cu) was heated by an UV laser beam transmitted through the glass substrate. The laser energy absorbed on the pad raised the temperature of a solder ball which is in physical contact with the pad, forming a reflowed solder bump. The effects of the adhesion and top coating layer on the laser reflow soldering were studied by measuring temperature profile of the ball during the laser heating process. The results were discussed based on the measurement of reflectivity of the adhesion layer. In addition, the microstructures of solder bumps and their mechanical properties were examined.

• Journal of the Microelectronics and Packaging Society
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• v.18 no.4
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• pp.91-95
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• 2011

The light extraction efficiency in GaN based LED was analyzed qualitatively. The extraction efficiency was simulated with patterned shape, depth, size and spacing by using ray-tracing simulation. In simulation result, patterned shape and depth for the optimized extraction efficiency in PSS LED were in indented Hemi-sphere solid. Through the optimal patterning of the various factors, about 40% enhancement in extraction efficiency was obtained.

• Proceedings of the IEEK Conference
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• 2008.06a
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• pp.511-512
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• 2008

Micro-pads made of PDMS(polydimethylsiloane) can be mechanical shock or vibration absorber because of its contractibility. Fabrication of micro-pads and techniques of separation from substrate and attachment to new substrate are developed. Three micron thick PDMS pads were fabricated by imprinting lithography.

• Journal of the Microelectronics and Packaging Society
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• v.11 no.4 s.33
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• pp.49-53
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• 2004

Polymeric materials are widely used in the electronic industry as a common dielectric material or adhesive. The polymeric layer coated on Si substrate can be subjected to thermal stresses due to difference in thermal expansion coefficients. The mismatch in thermal properties between the polymeric layer and the substrate results in significant residual stresses. In this study, the thermal deformation is measured by a curvature measurement method using laser scanning, and the elastic modulus is calculated by an analytic model.

• Journal of the Microelectronics and Packaging Society
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• v.9 no.3
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• pp.1-6
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• 2002

A low temperature process technology of copper thin films has been developed by a chemical vapor deposition technology for multi-level metallzations in ULSI fabrication. The copper films were deposited on TiN/Si substrates in helium atmosphere with the substrate temperature between $130^{\circ}C$ and $250^{\circ}C$. In order to get more reliable metallizations, effects on the post-annealing treatment to the electrical properties of the copper films have been investigated. The Cu films were annealed at the $5 \times10^{-6}$ Torr vacuum condition and the electrical resistivity and the nano-structures were measured for the Cu films. The electrical resistivity of Cu films shown to be reduced by the post-annealing. The electrical resistivity of 2.0 $\mu \Omega \cdot \textrm{cm}$ was obtained for the sample deposited at the substrate temperature of $180^{\circ}C$ after vacuum annealed at $300^{\circ}C$. The resistivity variations of the films was not exactly matched with the size of the nano-structures of the copper grains, but more depended on the contamination of the copper films.

• Journal of the Microelectronics and Packaging Society
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• v.19 no.1
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• pp.25-32
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• 2012

Package for artificial satellite is to produce mass production for high package with reliability certification as well as develop SDRAM (synchronous dynamic RAM) module which has such as miniaturization, mass storage, and high reliability in space environment. It requires sophisticated technology with chip stacking or package stacking in order to increase up to 4Gbits or more for mass storage with space technology. To make it better, we should secure suitable processes by doing design, manufacture, and debugging. Pin type PCB substrate was then applied to QFP-Pin type 3D memory package fabrication. These results show that the 3D memory package for artificial satellite scheme is a promising candidate for the realization of our own domestic technologies.

• ETRI Journal
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• v.33 no.5
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• pp.802-805
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• 2011

This letter presents a K-band polarization reconfigurable antenna integrated with a silicon radio frequency MEMS switch into the form of a compact package. The proposed antenna can change its state from linear polarization (LP) to circular polarization (CP) by actuating the MEMS switch, which controls the configuration of the coupling ring slot. Low-loss quartz is used for a radiating patch substrate and at the same time for a packaging lid by stacking it onto the MEMS substrate, which can increase the system integrity. The fabricated antenna shows broadband impedance matching and exhibits high axial ratios better than 15 dB in the LP and small axial ratios in the CP, with a minimum value of 0.002 dB at 20.8 GHz in the K-band.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.180-182
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• 2002

Copper thin films are prepared by a chemical vapor deposition technology for multi-level metallzations in ULSI fabrication. The copper films were deposited on TiN/Si substrates in helium atmosphere with the substrate temperature between $120^{\circ}C$ and $300^{\circ}C$. In order to get more reliable metallizations, effects on the post-annealing treatment to the electrical properties of the copper films have been investigated. The Cu films were annealed at the $5\times$10^{-6}$ Torr vacuum condition, and the electrical resistivity and the nano-structures were measured for the Cu films. The electrical resistivity of Cu films shown to be reduced by the post-annealing. The electrical resistivity of 2.2 $\mu$$\Omega$.cm was obtained for the sample deposited at the substrate temperature of $180^{\circ}C$ after vacuum annealed at $300^{\circ}C$. The resistivity variations of the films was not exactly matched with the size of the nato-structures of the copper grains, but more depended on the deposition temperature of the copper films.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.270-273
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• 2002

Conditioning은 CMP(Chemical Mechanical Planarization)에 필수적인 공정중의 하나이다. Conditioning의 목적은 removal rate와 uniformity를 CMP 공정 중에서 일정하게 유지시키는데 목적이 있다. 예전의 conditioning disks는 stainless steel substrate 위에 diamond 입자를 올리고 Ni전기도금을 결합시켜서 사용하였다. 그러나, CMP 공정 중에 Ni의분해로 인한 금속의 오염과 diamond abrasive의 분리로 인하여 scratch 문제가 발생하였다. 이 문제를 해결하기 위해서 ceramic substrate와 그것을 정밀 가공하는 기술을 응용함으로써 본래의 conditioning disks가 가지고 있는 diamond 입자의 분리와 metals 분해의 문제를 해결할 수 있게 되었다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.92-97
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• 2002

We establish a visible light emission from porous polycrystalline silicon nano structure(PPNS). The PPNS layer are formed on heavily doped n-type Si substrate. 2um thickness of undoped polycrystalline silicon deposited using LPCVD (Low Pressure Chemical Vapor Deposition) anodized in a HF: ethanol(=1:1) as functions of anodizing conditions. And then a PPNS layer thermally oxidized for 1 hr at $900 ^{\circ}C$. Subsequently, thin metal Au as a top electrode deposited onto the PPNS surface by E-beam evaporator and, in order to establish ohmic contact, an thermally evaporated Al was deposited on the back side of a Si-substrate. When the top electrode biased at +6V, the electron emission observed in a PPNS which caused by field-induces electron emission through the top metal. Among the PPNSs as functions of anodization conditions, the PPNS anodized at a current density of $10mA/cm^2$ for 20 sec has a lower turn-on voltage and a higher emission current. Furthermore, the behavior of electron emission is uniformly maintained.