• KIEE International Transactions on Electrophysics and Applications
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• v.5C no.4
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• pp.176-179
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• 2005

The increasing demand for high density packaging technologies and the evolution to mixed digital and analogue devices has been the con-set of increasing research in thin film multi-layer technologies such as the passive components integration technology. In this paper, Cu and TaO thin film with RF sputtering was deposited for spiral inductor and MOM capacitor on the $SiO_2$/Si(100) substrate. MOM capacitor and spiral inductor were fabricated for L-C band pass filter by sputtering and lift-off. We are analyzed and designed thin films L-C passive components for band pass filter at 900 MHz and 1.8 GHz, important devices for mobile communication system. Based on the high-Q values of passive components, MOM capacitor and spiral inductors for L-C band pass filter, a low insertion loss of L-C passive components can be realized with a minimized chip area. The insertion loss was 3 dB for a 1.8 GHz filter, and 5 dB for a 900 MHz filter. This paper also discusses a analysis and practical design to thin-film L-C band pass filter.

• Proceedings of the Korean Institute of Electrical and Electronic Material Engineers Conference
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• 2007.06a
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• pp.33-33
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• 2007

SoP-L 공정은 유전율이 상이한 재료를 이용하여 PCB 공정이 가능하고 다른 packaging 방법에 비해 공정 시간과 비용이 절약되는 잠정이 있다. 본 연구에서는 SoP-L 기술을 이용하여 Si 기판의 함몰에 판한 공정의 안정도와 함몰 시 제작된 때턴의 특성의 변화에 대해 관찰 하였다. Si 기판의 함몰에 Active device를 이용하여 특성의 변화를 살펴보고 공정의 안정도를 확립하려 했지만 Active device는 측정 시 bias의 확보와 특성의 민감한 변화로 인해 비교적 측정이 용이하고 공정의 test 지표를 삼기 위해 passive device 를 구현하여 함몰해 보았다. Passive device 의 제작 과정은 Si 기판 위에 spin coating을 통해 PI(Poly Imide)를 10um로 적층한 후에 Cr과 Au를 seed layer로 증착을 하였다. 그리고 photo lithography 공정을 통하여 photo resister patterning 후에 전해 Cu 도금을 거쳐 CPW 구조로 $50{\Omega}$ line 과 inductor를 형성하였다. 제작 된 passive device의 함몰 전 특성 추출 data와 SoP-L공정을 통한 함몰 후 추출 data 비교를 통해 특성의 변화와 공정의 안정도를 확립하였다. 차후 안정된 SoP-L 공정을 이용하여 Active device를 함몰 한다면 특성의 변화 없이 size 룰 줄이는 효과와 외부 자극에 신뢰도가 강한 기판이 제작 될 것으로 예상된다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 1999.11a
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• pp.59-63
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• 1999

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2000.04a
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• pp.69-72
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• 2000

기판과의 동시소성에 의한 고주파 MCM-C(Multi-Chip-Module-Cofired)용 저항을 제작하고 6 GHz 까지의 RF 특성을 측정하였다. 기판은 저온 소성용 기판으로서 총 8층으로 구성하였으며, 7층에 저항체 및 전극을 인쇄하고 Via를 통하여 기판의 최상부까지 연결되도록 하였다 저항체 Pastes, 저항체의 크기, Via의 길이 변화에 따라서 저항의 RF 특성은 고주파일수록 더욱 DC 저항값에서부터 변화되는 양상을 보였다. 내부저항의 등가회로를 구현한 결과, 저항은 전송선로, Capacitance 성분이 혼재되어 있는 것으로 나타났으며 전극의 형태에 따라 Capacitance 성분이 많은 차이를 나타내었다.

• Proceedings of the International Microelectronics And Packaging Society Conference
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• 2002.05a
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• pp.165-168
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• 2002

본 연구에서는 칩인덕터 코어 소재로 사용되는 (NiCuZn)-ferrite를 습식합성법을 이용하여 나노크기의 초미세 분말을 합성하였으며, 합성된 (ZiCuZn)-ferrite 의 제조공정 및 전파기적 특성에 관하여 고찰하였다. 조성은 (N $i_{0.4-x}$C $u_{x}$Z $n_{0.6}$)$_{1+w}$ (F $e_2$ $O_4$)$_{1-w}$에서 x의 값을 0.05~0.25 범위로 변화시켰으며, w 값은 0.03으로 고정하였다. 소결은 8$50^{\circ}C$에서 9$50^{\circ}C$의 범위에서 진행하였다. 나노크기의(NiCuZn)-ferrite를 사용함으로서 시약급 원료로 제조된 것보다 소결온도를 낮출 수 있었고, 밀도가 높은 페라이트 소결체를 얻을 수 있었다. 또한 초투자율, 품질계수 등 전자기적 특성이 우수하게 나타났다. 그 밖에 습식합성법으로 합성한 (NiCuZn)-ferrite 의 결정성, 미세구조 등을 XRD, SEM 을 이용하여 고찰하였다.하였다.다.

• Proceedings of the KIEE Conference
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• 2006.07c
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• pp.1301-1302
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• 2006

In this paper, embedded spiral inductors are investigated into the PCB substrate for low cost RF SOP applications. The spiral inductors designed with geometrical variations were simulated, fabricated, measured, and characterized by using 3D EM simulator, 8 layered PCB standard process and HP 8510B network analyzer (or verifying their applicability. The fabricated embedded spiral inductor has inductance of 9.4 nH at 800MHz, maximum quality factor of 64.8 at 1.09GHz and self resonant frequency of 3.93GHz, respectively. As the measured inductances and quality factors are well matched with simulated ones. PCB embedded spiral inductors are promising for advanced electronic systems with various functionality, low cost, small size and volume.

• Journal of the Microelectronics and Packaging Society
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• v.15 no.1
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• pp.59-64
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• 2008

Recently, DC-DC choppers must be increased switching frequency in order to achieve a small size, a light weight and a low noise. However, the switches of chopper are subjected to high switching power losses and switching stresses. As a result of these, the chopper system bring on a low power efficiency. To improved these, this paper is studied on a new DC-DC chopper of high efficiency operated with soft switching(that is, zero current switching and zero voltage switching, ZVCS), of semiconductor switches using in chopper. The soft switching operation is applied to a partial resonant method that the switches operate at zero current of inductor and zero voltage of capacitor in resonant circuit. And the partial resonant circuit makes use of a inductor using step-up and a snubber capacitor, the circuit topology of chopper is simple. Some simulative results on computer and experimental results confirm the validity of analytical results of the DC-DC chopper.

• Journal of the Microelectronics and Packaging Society
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• v.7 no.1
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• pp.1-5
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• 2000

Co-fired resistors for high frequency MCM-C (Multi Chip Module-Cofired) were fabricated and measured their RF properties from DC to 6 GHz. LTCC (Low Temperature Co-fired Ceramics) substrates with 8 layers were used as the substrates. Resisters and electrodes were printed on the 7th layer and connected to the top layer by via holes. Deviation from DC resistance of the resistors was resulted from the resister pastes, resistor size, and via length. From the experimental results, the suitable equivalent circuit model was adopted with resistor, transmission line, capacitor, and inductor. The characteristic impedance $Z_{o}$ of the transmission line from the equivalent circuit can explain the RF behavior of the buried resistor according to the structural variation.

• Journal of the Microelectronics and Packaging Society
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• v.28 no.2
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• pp.81-88
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• 2021

In this paper, by applying LTCC substrate, the library of the passive elements is implemented. And it can be used in 24 GHz circuits. Depending on how to use it to the circuit, it is required large value by designing the basic structures such as electrode capacitor and spiral inductor. However they are not available in high-frequency domain, because their SRF(Self-Resonant Frequency) is lower than the frequency of 24-GHz. By solving the limit, this paper devised passive elements classified for the DC and the high-frequency domain. The basic structure is suitable for low frequency under 1~2 GHz like DC. The microstrip λ/8 length stub structure is proposed to use for high-frequency like 24-GHz. The open and short stub structure operate as a capacitor and inductor respectively, also they have their impedances. Through their impedances, we can extract the value with the impedance-related equation. In this paper, the proposed passive elements are produced with the permittivity 7.5 LTCC substrate, the basic structure which are available in the DC constituted a library of capacitance of 2.35 to 30.44 pF and inductance of 0.75 to 5.45 nH, measured respectively. The stub structure available in the high-frequency domain were built libraries of capacitance of 0.44 to 2.89 pF and inductance of 0.71 to 1.56 nH, calculated respectively. The measurements have proven how to diversify value, so libraries can be built more variously. It will be an alternative to the passive elements that it is possible to integrate with the operation circuit of radar module for the frequency 24-GHz.

• Journal of the Microelectronics and Packaging Society
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• v.20 no.4
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• pp.75-79
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• 2013

A power distribution network (PDN) is a network that provides connection between the voltage source supply and the power/ground terminals of a microprocessor chip. It consists of a voltage regulator module, a printed circuit board, a package substrate, a microprocessor chip as well as decoupling capacitors. For power integrity analysis, the board and package layouts have to be transformed into an electrical network of resistor, inductor and capacitor components which may be expressed using the S-parameters models. This modeling process generally takes from several hours up to a few days for a complete board or package layout. When the board and package layouts change, they need to be re-extracted and the S-parameters models also need to be re-generated for power integrity assessment. This not only consumes a lot of resources such as time and manpower, the task of PDN modeling is also tedious and mundane. In this paper, a block-based PDN modeling is proposed. Here, the board or package layout is partitioned into sub-blocks and each of them is modeled independently. In the event of a change in power rails routing, only the affected sub-blocks will be reextracted and re-modeled. Simulation results show that the proposed block-based PDN modeling not only can save at least 75% of processing time but it can, at the same time, keep the modeling accuracy on par with the traditional PDN modeling methodology.