• Proceedings of the KIEE Conference
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• 2003.10a
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• pp.151-159
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• 2003

According to the records, approximately 50 percent of power failure were caused by lightning. Conventional fault preventive measures against lightning include reduction of the footing resistance of the tower, multiplication of overhead ground wires and unbalanced insulation of the double circuit transmission tower. In addition to these, transmission line arresters have been recently appeared as an alternatives. In this paper an unbalanced insulation method with transmission line arrester was assumed as another countermeasure against simultaneous double circuit trip of 154 kV transmission line by lightning strike. The lightning performance of line arrester was compared with conventional insulation concept using different numbers of porcelain and glass insulator. Larger numbers of insulator simply increase flashover current level by lightning but the lightning performance doesn't proportional to it. EMTP simulation and predictive calculation of lightning failure rate were carried out to evaluate the performance.

• Journal of Korea Multimedia Society
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• v.14 no.11
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• pp.1420-1430
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• 2011

This paper proposes a new method to optimize energy consumption in a wireless modem by setting up a transmission power value according to the distance between nodes and circumstance in the MAC layer of IEEE 802.15.4. The proposed method can dynamically find an optimal transmission power range using the binary search scheme and minimize overhead caused by multiple message transmissions when determining the optimal transmission power. The determined transmission power is used for transmitting data packets and can be modified dynamically depending on the changes in a network environment when exchanging data packets and acknowledgement signals. The results of the simulations show 30% reduction in energy consumption while 2.5 times increase in data transmission rate per unit of energy comparing with IEEE 802.15.4 standard.

• JSTS:Journal of Semiconductor Technology and Science
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• v.15 no.5
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• pp.476-484
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• 2015

Due to the recent advances in non-volatile memory technologies such as PCM, a new memory hierarchy of computer systems is expected to appear. In this paper, we explore the performance of PCM-based swap systems and discuss how this system can be managed efficiently. Specifically, we introduce three management techniques. First, we show that the page fault handling time can be reduced by attaching PCM on DIMM slots, thereby eliminating the software stack overhead of block I/O and the context switch time. Second, we show that it is effective to reduce the page size and turn off the read-ahead option under the PCM swap system where the page fault handling time is sufficiently small. Third, we show that the performance is not degraded even with a small DRAM memory under a PCM swap device; this leads to the reduction of DRAM's energy consumption significantly compared to HDD-based swap systems. We expect that the result of this paper will lead to the transition of the legacy swap system structure of "large memory - slow swap" to a new paradigm of "small memory - fast swap."

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.38 no.10
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• pp.10-17
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• 2001

For high-speed Internet services, considerations on interworking methods are required for interworking between networks with different technologies. lnterworking and structures in interworking point nodes can affect on transfer efficiency. This paper proposes interworking procedures and functions of the edge routers for overhead reduction in MPOA-MPLS networks. The MPLS networks can be based on ATM technology. Therefore, we consider ATM seamless connections for the interworking and compare the proposed method with that without seamless connection. We perform computer simulations to get both of the transfer delays and throughputs for the comparison., we describe required interworking functions and operations in the edge routers.

• Journal of the Korean Institute of Telematics and Electronics C
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• v.35C no.6
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• pp.48-55
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• 1998

In this work, the testable CAM(Content Addressable Memory) is designed to perform the test effectively by inserting the ECC(Error Checking Circuit) inside the CAM. The designed CAM has the circuit which is capable of testing the functional faults in read, write, and match operations. In general the test circuit inserted causes the increase of total circuit area, Thus this work, utilizes the new MTA code to reduce the overhead of an area of the built-in test circuit which has a conventional parallel comparator. The designed circuit was verified using the VHDL simulator and the layout was performed using the 0.8${\mu}{\textrm}{m}$ double metal CMOS process. About 30% reduction of a circuit area wad achieved in the proposed CAM using the XOR circuit

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2A
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• pp.140-146
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• 2004

In this paper we proposed the reducing method of feedback information for transmitting of adaptable data rate in multi-user OFDMA/FDD systems. In order to transmit downlink channel information to Base-Station(BS) through the limited uplink control channel, the proposed algorithm exploits the channel variation level which describes the similarity among the adjacent clusters and uses just one modulation and coding scheme(MCS) level representing channel information of all clusters'. We investigated the performance in single cell environment. It has a similar overhead for feedback information with conventional algorithm and has better performance in that bandwidth efficiency and outage probability than the conventional algorithms.

• Journal of the Society of Disaster Information
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• v.4 no.2
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• pp.138-154
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• 2008

The conventional non-dig underground structure building method which made an appearance to reduce the social and environmental costs and maximize the efficiency of the social overhead capital facilities could not help being uneconomical because of many problems such as unnecessary excessive excavation, water leakage, obstacle interference, difficulty of curvilinear application and connection complexity between propelled and injected bodies due to indiscriminate application of small and large circular steel pipes without consideration of the site conditions. The T.S.T.M, in which a protruded square tube is applied as a propulsion and injection body in a design that considered site conditions such as ground condition, depth of soil and live load, was able to be economical as it solved the problems of water resistance, minimization of obstacle interference and curvilinearity, and we can see that it can be applied to all grounds by utilizing or complementing the target ground in terms of engineering. Also in configuring the transverse section, it is possible to not only secure excellent structural safety but also implement all of the above engineering characteristics not only in the square cross section but also in the arch cross section, so it was possible to build structures on any section or ground, and we could confirm the LCC reduction effect and the VE effect.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.29 no.2C
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• pp.298-305
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• 2004

This paper presents an error compensation method for a fixed-width modified Booth multiplier that receives a W-bit input and produces a W-bit product. To efficiently compensate for the quantization error, Booth encoder outputs (not multiplier coefficients) are used for the generation of error compensation bias. The truncated bits are divided into two groups depending upon their effects on the quantization error. Then, different error compensation methods are applied to each group. By simulations, it is shown that quantization error can be reduced up to 50％ by the proposed error compensation method compared with the existing method with approximately the same hardware overhead in the bias generation circuit. It is also shown that the proposed method leads to up to 40％ reduction in area and power consumption of a multiplier compared with the ideal multiplier.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.4
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• pp.395-404
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• 2016

A 6-bit 3.4 GS/s flash ADC in a 65 nm CMOS process is reported along with the proposed 4x time-domain interpolation technique which allows the reduction of the number of comparators from the conventional $2^N-1$ to $2^{N-2}$ in a N-bit flash ADC. The proposed scheme effectively achieves a 4x interpolation factor with simple SR-latches without extra clocking and calibration hardware overhead in the interpolated stage where only offset between the $2^{N-2}$ comparators needs to be calibrated. The offset in SR-latches is within ${\pm}0.5$ LSB in the reported ADC under a wide range of process, voltage supply, and temperature (PVT). The design considerations of the proposed technique are detailed in this paper. The prototype achieves 3.4 GS/s with 5.4-bit ENOB at Nyquist and consumes 12.6 mW power at 1 V supply, yielding a Walden FoM of 89 fJ/conversion-step.

• Journal of the Korea Society of Computer and Information
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• v.15 no.5
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• pp.93-101
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• 2010

Although various network management architectures such as centralized, distributed, and hybrid have been presented, any one is not always efficient in all the environment. In this paper, we propose a hierarchical and split network management architecture based on MA+SNMP in order to manage a network of many small NEs distributed over the wide area. Our hierarchical architecture has MA-based proxy management nodes for the flexibility and overhead reduction in NMS as well as SNMP-based NEs considering NE's capacity. Through the analysis with real experiments, we show that our proposal improves some drawbacks and the processing delay of the existing architectures in the given environment.