• Fire Science and Engineering
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• v.30 no.6
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• pp.92-98
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• 2016

This study evaluated thermal image real-time estimation and fire alarm using by a CCD camera, which has been a seamless feature-point analysis method, according to the angle and position and image fusion by a vector coordinate point set-up of equal shape. The system has higher accuracy, fixing data value of temperature sensing and fire image of 0~255, and sensor output-value of 0~5,000. The operation time of a flame specimen within 500 m, 1000 m, and 1500 m from the test report specimen took 7 s, 26 s, and 62 s, respectively, and image creation was proven. A diagnosis of fire accident was designated to 3 steps: Caution/Alarm/Fire. Therefore, a series of process and the transmission of SNS were identified. A light bulb and fluorescent bulb were also tested for a false alarm test, but no false alarm occurred. The possibility that an unwanted alarm will be reduced was verified through a forecast of the fire progress or real-time estimation of a thermal image by the change in the image of a time-based flame and an analysis of the diffusion velocity.

• The Journal of Society for e-Business Studies
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• v.7 no.1
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• pp.87-106
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• 2002

The behavioral and dynamic implications of an ERP implementation/installation are, to say the least, not well understood. Getting the switches set to enable the ERP software to go live is becoming straightforward. The really difficult part is understanding all of the dynamic interactions that accrue as a consequence. Dynamic causal and connectionist models are employed to facilitate an understanding of the dynamics and to enable control of the information-enhanced processes to take place. The connectionist model ran be analyzing (behind the scenes) the information accesses and transfers and coming If some conclusions about strong linkages that are getting established and what the behavioral implications of those new linkages and information accesses we. Ultimately, the connectionist model will come to an understanding of the dynamic, behavioral implications of the larger ERP implementation/installation per se. The underlying connectionist model will determine information transfers and workflow. Once a map of these two infrastructures is determined by the model, it becomes a relatively easy job for an analyst to suggest improvements in both. Connectionist models start with analog object structures and then use learning to produce mechanisms for managerial problem diagnoses. These mechanisms are neural models with multiple-layer structures that support continuous input/output. Based on earlier work performed and published by the author[10][11], a Connectionist ReasOning and LEarning System(CROLES) is developed that mimics the real-world reasoning infrastructure. Coupled with an explanation subsystem, this system can provide explanations as to why a particular reasoning structure behaved the way it did. Such a system operates in the backgmund, observing what is happening as every information access, every information response coming from each and every intelligent node (whether natural or artificial) operating within the ERP infrastructure is recorded and encoded. The CROLES is also able to transfer all workflows and map these onto the decision-making nodes of the organization.

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.38 no.10
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• pp.754-764
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• 2001

Class A bipolar second-generation current conveyor (CCII) with low current-input impedance and its offset-compensated CCII for high-accuracy current-mode signal processing are proposed. The CCIIs consist of a regulated current-cell for current input, a emitter follower for voltage input, and a cascode current mirror lot current output. In these architecture, the two input stages are coupled by current mirror to reduce the current input impedance. Experiments show that the CCII has impedance of 8.4 Ω and offset voltage of 40 mV at current input terminal. To reduce this offset, the offset-compensated CCII adopts diode-connected npn and pnp transistor in the proposed CCII. Experiments show that the offset-compensated CCII has current input impedance of 2.1 Ω and offset voltage of 0.05 mV. The 3-dB cutoff frequency of the CCIIs when used as a voltage follower extends beyond 30 MHz. The power dissipation is 7.0 mW

• Journal of the Institute of Electronics Engineers of Korea SD
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• v.39 no.6
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• pp.26-33
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• 2002

In this paper, a new four-quadrant MOS analog multiplier Is proposed using the quarter-square technique, which is based on the quadratic characteristics of MOS transistor operating in the saturation region and the difference operation of a source-coupled differential circuits. The proposed circuit has been fabricated in a p-well CMOS process. The multiplier achieves a total harmonic distortion of less than 1 percent for the both input ranges of 50 percent of power supply, a -3㏈ bandwidth of 30㎒ a dynamic range of 81㏈ and a power consumption of 40㎽. The active chip area is 0.54㎟. The supposed multiplier circuit is simple and adjust high frequency application because one input signal transfer output by one transistor.

• Journal of IKEEE
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• v.14 no.1
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• pp.8-16
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• 2010

This paper presents a design of the successive approximation ADC(SA-ADC) applicable to a midium-low speed analog-front end(AFE) for the maximum 15MS/s CCD image processing. SA-ADC is effective in applications ranging widely between low and mid data rates due to the large power scaling effect on the operating frequency variations in some other way of pipelined ADCs. The proposed design exhibits some distinctive features. The "differential capacitor-coupling scheme" segregates the input sampling behavior from the sub-DAC incorporating the differential input and the sub-DAC output, which prominently reduces the loading throughout the signal path. Determining the MSB(sign bit) from the held input data in advance of the data conversion period, a kind of the signed successive approximation, leads to the reduction of the sub-DAC hardware overhead by 1 bit and the conversion period by 1 cycle. Characterizing the proposed design in a 3.3 V $0.35-{\mu}m$ CMOS process by Spectre simulations verified its validity of the application to CCD analog front-ends.

• Journal of Korean Tunnelling and Underground Space Association
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• v.13 no.3
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• pp.199-214
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• 2011

A crack is the main cause to affect the integrity of tunnel lining as well as leakage, spalling, exposed rebar, corrosion, carbonation and so on. Since the 1980, NATM has prevailed on excavation method and geotechnical philosophy in tunnel. Although the pattern of cracks has been reported by several engineers' effort, it was only focused on longitudinal cracks of lining. Eleven operational NATM tunnels have been conducted with the precise inspection for safety and diagnosis by KISTEC (Korea Infrastructure Safety and Technology Incorporation). With those results, the crack patterns by the spatial distribution and appearance for each tunnel have been analyzed and the cause of occurrence for seven common types of cracks in NATM tunnels was classified. Additionally, the longitudinal crack on lining above duct slab was figured out by numerical simulation and field inspection. Each crack has been analyzed by CCD (Charge-Coupled Device) scanner image with 3D configuration. Each type of cracks is also explained with output of experimental and condition of construction. Defined cracks on NATM tunnels will be good example for periodical inspection and precise inspection for safety and diagnosis.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.1
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• pp.34-40
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• 2004

The PLDRO(Phase-Locked Dielectric Resonator Oscillator) with low phase noise is designed for X-band. The phase of VCDRO(Voltage Controlled Dielectric Resonator Oscillator) is locked to that of a high stable reference oscillator by using a SPD(Sampling Phase Detector) to improve phase noise performance in the loop bandwidth. And, the VCDRO is implemented using a high impedance inverter coupled with dielectric resonator to improve the phase noise performance out of the loop bandwidth. This PLDRO exhibits the harmonic rejection characteristics of 51.67㏈c and requires below 1.95W. The phase noise characteristics are performed as -107.17㏈c/Hz at 10KHz offset frequency and -113.0㏈c/Hz at 100KHz offset frequency, respectively, at ambient. And the output power of 13.0㏈m${\pm}$0.33㏈ is measured over the temperature range of $-20 ∼ +70^{\circ}C$ .

• Journal of Electrical Engineering and Technology
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• v.9 no.1
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• pp.301-306
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• 2014

We proposed a new PCB-type 'common-mode current($I_c$) and differential-mode current($I_d$) detector' working for fast detection of $I_c$ and $I_d$ from the differential-mode signaling, with miniaturization effect and possibility of cheaper fabrication. In order to realize this device, we suggest a branch-line-coupler balun having a composite right- and left-handed(CRLH) one-layer microstrip phase-shifting line as compact as roughly ${\lambda}_g/14$. The presented balun obviously is different from the conventional bent-&-folded delay lines or slits on the ground for coupling the lines on the top and bottom dielectrics. As we connect the suggested balun output ports of the differential-mode signal lines via the through-port named U and coupled-port named L, $I_c$ and $I_d$ will appear at port ${\Delta}$ and port ${\Sigma}$ of the present device, in order. The validity of the design scheme is verified by the circuit-and numerical electromagnetic analyses, and the dispersion curve proving the metamaterial characteristics of the geometry. Besides, the examples of the $I_c$ and $I_d$ indicator are observed as the even and odd modes in differential-mode signal feeding. Also, the proposed device is shown to be very compact, compared with the conventional structure.

• Journal of the Korean Society for Aeronautical & Space Sciences
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• v.31 no.5
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• pp.18-24
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• 2003

The design cycle associated with large engineering systems requires an initial decomposition of the complex system into design processes which are coupled through the transference of output data. Some of these design processes may be grouped into iterative sybcycles. Previous researches predifined the numbers of design processes in groups, but these group sizes should be determined optimally to balance the computing time of each groups. This paper proposes adaptive decomposition method, which determines the group sizes and the order of processes simultaneously to raise design efficiency by expanding the chromosome of the genetic algorithm. Finally, two sample cases are presented to show the effects of optimizing the sequence of processes with the adaptive decomposition method.

• Transactions of the Society of Information Storage Systems
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• v.1 no.2
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• pp.155-160
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• 2005

In this paper, the channel decoder promising reliable data retrieving in noisy holographic channel has been developed for holographic WORM(write once read many) system. It covers various DSP(digital signal processing) blocks, such as align mark detector, adaptive channel equalizer, modulation decoder and ECC(error correction code) decoder. The specific schemes of DSP are designed to reduce the effect of noises in holographic WORM(H-WORM) system, particularly in prototype of DAEWOO electronics(DEPROTO). For real time data retrieving, the channel decoder is redesigned for FPGA(field programmable gate array) based hardware, where DSP blocks calculate in parallel sense with memory buffers between blocks and controllers for driving peripherals of FPGA. As an input source of the experiments, MPEG2 TS(transport stream) data was used and recorded to DEPROTO system. During retrieving, the CCD(charge coupled device), capturing device of DEPROTO, detects retrieved images and transmits signals of them to the FPGA of hardware channel decoder. Finally, the output data stream of the channel decoder was transferred to the MPEG decoding board for monitoring video signals. The experimental results showed the error corrected BER(bit error rate) of less than $10^{-9}$, from the raw BER of DEPROTO, about $10^{-3}$. With the developed hardware channel decoder, the real-time video demonstration was possible during the experiments. The operating clock of the FPGA was 60 MHz, of which speed was capable of decoding up to 120 mega channel bits per sec.