• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.5
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• pp.988-994
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• 2004

In this paper we analyze the effects of frequency offset, doppler spread, sampling and oscillator phase noise in mobile channels on orthogonal frequency division multiplexing(OFDM)system, Since this kind of distortions cause subcarrier interference which can be seen as additional noise, performance of OFDM system is degraded. We show the limitation of maximum carrier frequency offset and doppler frequency to maintain designated SNR, and analyze characteristics of the performance of OFDM systems considering the oscillator phase noise.

• International journal of advanced smart convergence
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• v.10 no.1
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• pp.12-23
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• 2021

This paper proposes a low power radio frequency receiver front-end where, in a single stage, single-balanced mixer and voltage-controlled oscillator are stacked on top of low noise amplifier and re-use the dc current to reduce the power consumption. In the proposed topology, the voltage-controlled oscillator itself plays the dual role of oscillator and mixer by exploiting a series inductor-capacitor network. Using a 65 nm complementary metal oxide semiconductor technology, the proposed radio frequency front-end is designed and simulated. Oscillating at around 2.4 GHz frequency band, the voltage-controlled oscillator of the proposed radio frequency front-end achieves the phase noise of -72 dBc/Hz, -93 dBc/Hz, and -113 dBc/Hz at 10KHz, 100KHz, and 1 MHz offset frequency, respectively. The simulated voltage conversion gain is about 25 dB. The double-side band noise figure is -14.2 dB, -8.8 dB, and -7.3 dB at 100 KHz, 1 MHz and 10 MHz offset. The radio frequency front-end consumes only 96 ㎼ dc power from a 1-V supply.

• Journal of the Institute of Electronics and Information Engineers
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• v.51 no.2
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• pp.19-22
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• 2014

In this paper, Ku-band low phase noise oscillator using DSRR structure resonator based on metamaterial was proposed. To improve the phase noise of the oscillator, the proposed resonator consist of a DSRR strcuture based on metamaterial. The proposed resonator have a characteristic of $S_{11}$ is -0.25 dB, and $S_{21}$ in -44.59 dB at 14.67 GHz, respectively. At 14.67 GHz, the proposed Ku-band low phased oscillator achieves a output power of 2.03 dBm, $2^{nd}$ harmonic of -36.04 dBc, and phase noise of -130.63 dBc at the 100 kHz offset, respectively.

• Journal of the Institute of Electronics Engineers of Korea TC
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• v.47 no.8
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• pp.47-52
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• 2010

In this paper, a phase-locked loop with a self-noise suppressing voltage controlled oscillator to improve a phase noise characteristic has been proposed. The magnitude of the proposed transfer function is maximum 25dB lower than that of a conventional transfer function around a bandwidth. The proposed PLL has been designed based on a 1.8V $0.18{\mu}m$ CMOS process and proved by HSPICE simulation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.11
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• pp.1272-1280
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• 2008

In this paper, we have proposed a phase noise model of fast frequency hopping synthesizer with DDS Driven PLL architecture. To accurately model the phase noise contribution of noise sources in frequency hopping synthesizer, they were investigated using model of digital divider for PLL, DAC for DDS and Leeson's model for reference oscillator and VCO. Especially it was proposed that the noise component of low pass filter was considered together with the phase noise of VCO. Under assuming linear operation of a phase locked loop, the phase noise transfer functions from noise sources to the output of synthesizer was analyzed by superposition theory. The proposed phase noise prediction model was evaluated and its results were compared with measured data.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.967-973
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• 2009

In this paper, X-band satellite communication oscillator of double phase locked is implemented by constructing a couple of phased-locked loop, and then we have analyzed the phase noise of designed PLL-DRO. The designed phase-locked oscillator is consist of series feedback DRO, frequency divider, phase detector, loop filter and programmable PLL-IC. By dividing oscillation frequency of 12.6 GHz into two frequencies, it exhibits output power of 15.32 dBm at 6.3 GHz. Phase noises of implemented oscillator are -81 dBc/Hz@100Hz, -100.86 dBc/Hz@1 kHz, -111.12 dBc/Hz@10 kHz, -116 dBc/Hz@100 kHz and -140.49 dBc/Hz@1 MHz respectively. These indicate excellent stable operation of oscillator and very good phase noise characteristics.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.19 no.2
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• pp.152-160
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• 2008

In this paper, we analyze the performance of a direct-conversion UHF RFID reader with the range correlation effects of the phase noise. Since a UHF RFIB system uses the same oscillator to generate the transmitted carrier and the local oscillation, the periodic interference and phase noise reduction effects occur due to time delay between two signals. Through exact theory and simulation, we verify how to cancel the periodic interference phenomena using I/Q diversity combining technique. And, we analyze phase noise reduction effects due to range correlation as a function of the tag-reader distance and the offset frequency Using these results, we simulate the symbol-error-rate performance with respect to phase noise with and without range correation effects. We show that the phase noise of the local oscillator has little effect on the symbol-error-rate performance because of phase noise reduction by range correlation.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.13 no.7
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• pp.649-656
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• 2002

This paper addresses the phase noise analysis of high-speed DH-PLL(Digital Hybrid Phase-Locked Loops) frequency synthesizer. Because of the additional quantization noise of D/A converter in DH-PLL, the phase noise of DH-PLL is increased than the conventional PLL. Three kinds of noise sources such as reference input, D/A converter, and VCO(Voltage Controlled Oscillator) are considered to analyze the phase noise. It largely depends on the closed loop bandwidth and frequency synthesis division ratio(N) so that we can decide the optimal closed loop bandwidth to minimize the phase noise of DH-PLL. It is shown that the simulation results closely match with the results of analytical approach.

• Journal of the Korean Institute of Telematics and Electronics
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• v.13 no.5
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• pp.24-29
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• 1976

In the phase locked AM signal detection, phase locked loop is used to extract a synchronous carrier from an input AM signal. Under the assumption that input noise is white Gaussian and free-running frequency of voltage controlled oscillator is the same that of an input carrier, operational behaviours of phase locked loop is analyzed and signal to noise ratio of the detection is derived quentitatively. The results show that the phase locked AM signal detection method offers a higher degree of noise mmunity than conventional AM signal detections.

• ETRI Journal
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• v.33 no.1
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• pp.125-127
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• 2011

This letter presents a new type of resonator, namely, the split quarterwave microstrip resonator (SQMR), to improve the poor harmonic suppression and low Q-factors in conventional quarterwave microstrip resonators. An oscillator incorporating the proposed SQMR is designed, fabricated, and tested to demonstrate that, not only the second harmonic suppression, but also the phase noise of the oscillator can be improved. The oscillator with the SQMR shows improved second harmonic suppression of -74.59 dBc and phase noise figure of merit of -169.77 dBc/Hz at 1 MHz offset.