• Journal of the Korea Institute of Information and Communication Engineering
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• v.11 no.12
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• pp.2205-2209
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• 2007

In this paper, a voltage controlled oscillator(VCO) of core components for wireless subscriber network is designed. The type of oscillator is colpits method and the oscillator device uses a LC resonator. The product is made on FR-4 substrate with dielectric constant of 4.6. The designed VCO is operated at 3.2V, 10mA and has output value of 0.67dB. The VCO's phase noise property is -102DBc/Hz at offset frequence of 100kHz. The fabricated VCO is the same as target value and can be used for wireless subscriber network.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.18 no.9
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• pp.2176-2182
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• 2014

In this paper, a phase locked loop with suppressed power supply noise has been proposed. The added negative feedback loop of voltage controlled oscillator(VCO) and power noise detector suppresses the power noise induced jitter variation of VCO down to 1/3. The power noise detector is the modified circuit of frequency voltage converter. The proposed PLL has been designed based on a 1.8V 0.18um CMOS process and proved by HSPICE simulation.

• Proceedings of the Korean Institute of Navigation and Port Research Conference
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• v.2
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• pp.385-390
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• 2006

This paper examines the sampling and jitter specifications and considerations for Global Navigation Satellite Systems (GNSS) software receivers. Software radio (SWR) technologies are being used in the implementation of communication receivers in general and GNSS receivers in particular. With the advent of new GPS signals, and a range of new Galileo and GLONASS signals soon becoming available, GNSS is an application where SWR and software-defined radio (SDR) are likely to have an impact. The sampling process is critical for SWR receivers, where it occurs as close to the antenna as possible. One way to achieve this is by BandPass Sampling (BPS), which is an undersampling technique that exploits aliasing to perform downconversion. BPS enables removal of the IF stage in the radio receiver. The sampling frequency is a very important factor since it influences both receiver performance and implementation efficiency. However, the design of BPS can result in degradation of Signal-to-Noise Ratio (SNR) due to the out-of-band noise being aliased. Important to the specification of both the ADC and its clocking Phase- Locked Loop (PLL) is jitter. Contributing to the system jitter are the aperture jitter of the sample-and-hold switch at the input of ADC and the sampling-clock jitter. Aperture jitter effects have usually been modeled as additive noise, based on a sinusoidal input signal, and limits the achievable Signal-to-Noise Ratio (SNR). Jitter in the sampled signal has several sources: phase noise in the Voltage-Controlled Oscillator (VCO) within the sampling PLL, jitter introduced by variations in the period of the frequency divider used in the sampling PLL and cross-talk from the lock line running parallel to signal lines. Jitter in the sampling process directly acts to degrade the noise floor and selectivity of receiver. Choosing an appropriate VCO for a SWR system is not as simple as finding one with right oscillator frequency. Similarly, it is important to specify the right jitter performance for the ADC. In this paper, the allowable sampling frequencies are calculated and analyzed for the multiple frequency BPS software radio GNSS receivers. The SNR degradation due to jitter in a BPSK system is calculated and required jitter standard deviation allowable for each GNSS band of interest is evaluated. Furthermore, in this paper we have investigated the sources of jitter and a basic jitter budget is calculated that could assist in the design of multiple frequency SWR GNSS receivers. We examine different ADCs and PLLs available in the market and compare known performance with the calculated budget. The results obtained are therefore directly applicable to SWR GNSS receiver design.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.20 no.9
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• pp.961-966
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• 2009

In this paper, a novel voltage-controlled oscillator(VCO) using the metamaterial broadside coupled spiral resonators(BC-DSRs) is presented for reducing the phase noise. For reducing of the phase noise, the series spiral structures have been applied for the signal plane and ground plane at each in order to have the large coupling. Compared with the conventional VCO, the proposed VCO has the larger coupling coefficient constant, which makes a higher Q-factor and has reduced the phase noise of the VCO. The proposed VCO has the phase noise of $-121{\sim}-117.16\;dBc$/Hz at 100 kHz in the tuning range, $5.749{\sim}5.853\;GHz$. The figure of merit(FOM) of this VCO is $-198.45{\sim}-194.77\;dBc$/Hz at 100 Hz in the same tuning range, respectively.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.8 no.4
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• pp.906-911
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• 2004

In this paper, a VCDRO(Voltage Control Dielectric Resonator Oscillator) applied to FMCW(Frequency Modulated Continuous Wave)Radar as stable source is implemented and constructed with a MESFET(Metal-semiconductor Field-Effect Transistor) for low noise, a dielectric resonate. of high frequency selectivity, and high Q varator diode to obtain a good phase noise performance and stable sweep characteristics. The designed circuits is simulated thrash harmonic balance simulation technique to provide the optimum performance. The measured result of a fabricated VCDRO shows that output is 2.22㏈m at 12.05GHz, harmonic suppression -30㏈c, phase noise -130㏈c at 100KHz offset, and sweep range of varator diode $\pm$18.7MHz, respectively. This oscillator will be available to FMCW Radar.

• JSTS:Journal of Semiconductor Technology and Science
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• v.13 no.4
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• pp.272-281
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• 2013

This paper presents low power frequency shift keying (FSK) transmitter using all digital PLL (ADPLL) for smart utility network (SUN). In order to operate at low-power and to integrate a small die area, the ADPLL is adopted in transmitter. The phase noise of the ADPLL is improved by using a fine resolution time to digital converter (TDC) and digitally controlled oscillator (DCO). The FSK transmitter is implemented in $0.18{\mu}m$ 1-poly 6-metal CMOS technology. The die area of the transmitter including ADPLL is $3.5mm^2$. The power consumption of the ADPLL is 12.43 mW. And, the power consumptions of the transmitter are 35.36 mW and 65.57 mW when the output power levels are -1.6 dBm and +12 dBm, respectively. Both of them are supplied by 1.8 V voltage source. The frequency resolution of the TDC is 2.7 ps. The effective DCO frequency resolution with the differential MOS varactor and sigma-delta modulator is 2.5 Hz. The phase noise of the ADPLL output at 1.8 GHz is -121.17 dBc/Hz with a 1 MHz offset.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.7 no.8
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• pp.1591-1597
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• 2003

In this paper, Active Resonator Oscillator using active inductor and active capacitor with HEMTs(agilent ATF­34143) is designed and fabricated. Active inductor with ­25$\Omega$ and 2.4nH in 5.5GHz frequency band and Active capacitor with ­14$\Omega$ and 0.35pF is designed. Active Resonator Oscillator for LO in ISM band(5.8GHz) is designed with active inductor and active capacitor. Active Resonator Oscillator has been simulated by Agilent ADS 2002C. Active Resonator oscillator implemented on the substrate which has the relative dielectric constant of 3.38, the height of 0.508mm, and metal thickness of 0.018mm. This Active Resonator Oscillator shows the oscillation frequency of 5.68GHz with the output power of ­3.6㏈m and phase noise of ­81㏈c/Hz at the offset frequency of 100KHz.

• The Journal of the Institute of Internet, Broadcasting and Communication
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• v.21 no.1
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• pp.107-114
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• 2021

In this paper, a planar transistor oscillator for X-band using a newly proposed L-shaped monopole slot resonator is proposed. For planar design, an L-shaped monopole slot with an open-end is used as a resonator for a transistor oscillator. As a result of the simulated design of the resonator in three stages, a high Q value of 1169.84 and a high insertion loss of 49.934 dB were identified. The results of the final design and manufactured oscillator measurements confirmed that the oscillation output is greater than 7 dBm and has good phase noise characteristics of -58 dBc/Hz at 100 kHz offset. The proposed oscillator is planar and has the advantage of being directly applicable to microwave integrated circuit technology. It also has the advantage of being able to reduce its size as it can only be implemented in microstrip form without additional devices such as metal cavities and tuning screws in 3D structures, as in the case of a DRO (dielectric resonance oscillator).

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.16 no.3 s.94
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• pp.319-326
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• 2005

In the multi-carrier OFDM communication system for the high data rate transmission, the ICI caused by phase noise of transceiver local oscillator may degrade the system performance seriously. In this paper, a new ICI self-cancellation scheme using data-conjugate method is proposed to reduce the ICI caused by phase noise effectively. Then, the CPE, ICI and CIR are derived by the phase noise linear approximation method. Besides, to analyze the efficiency of system performance improvement, the proposed method is compared with the original OFDM and the conventional ICI self-cancellation scheme using data-conversion method. As results, the performance degradation caused by ICI can be mitigated effectively in the OFDM system with ICI self-cancellation scheme, and more performance improvement can be achieved by the proposed ICI self-cancellation scheme using data-conjugate method than the conventional ICI self-cancellation scheme using data-conversion method when phase noise exists.

• Proceedings of the Korea Electromagnetic Engineering Society Conference
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• 2001.11a
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• pp.218-221
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• 2001

In this paper, High Q Inductor using negative resistance circuit and the ceramic inductor was designed and fabricated at 2GHz. It was Improved the inductor of Q=90 using a inductor with Q=30 added to negative resistance circuit at 2GHz. As a result, at the bias condition of 3V and 16mA, the output power and phase noise in the operation frequency 2.01GHz are 5dBm and -115.34dBc/Hz at 100kHz offset from carrier, respectively. Phase noise was improved -10dBc/Hz at 100kHz offset compared to only using ceremic inductor.