• Journal of IKEEE
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• v.23 no.4
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• pp.1314-1320
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• 2019

In this paper, we propose a new method for optimizing bit operations and applying them to DNN(Deep Neural Network) in software environment. As a method for this, we propose a packing function for bitwise optimization and a masking matrix multiplication operation for application to DNN. The packing function converts 32-bit real value to 2-bit quantization value through threshold comparison operation. When this sequence is over, four 32-bit real values are changed to one 8-bit value. The masking matrix multiplication operation consists of a special operation for multiplying the packed weight value with the normal input value. And each operation was then processed in parallel using a GPU accelerator. As a result of this experiment, memory saved about 16 times than 32-bit DNN Model. Nevertheless, the accuracy was within 1%, similar to the 32-bit model.

• Journal of Power Electronics
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• v.9 no.2
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• pp.232-242
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• 2009

In this paper, a matrix converter with improved low frequency output performance is proposed by achieving a one-step commutation owing to a general commutation circuit applicable to n-phase to m-phase matrix converters. The commutation circuit consists of simple resister and capacitor components, leading to a very stable, reliable and robust operation. Also, it requires no extra sensing information to achieve commutation, allowing for a one-step commutation like a conventional dead time commutation. With the dead time commutation strategy applied, the distortion caused by commutation delay is analyzed and compensated, therefore leading to better output linear behavior. In this paper, detailed commutation procedures of the R-C commutation circuit are analyzed. A selection of specific semiconductor switches and commutation circuit components is also provided. Finally, the effectiveness of the proposed commutation method is verified through a two-phase to single-phase matrix converter and the feasibility of the compensation approach is shown by an open loop space vector modulated three-phase matrix converter with a passive load.

• Journal of Electrical Engineering and Technology
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• v.5 no.2
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• pp.299-306
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• 2010

This paper proposes a new doubly-fed induction generator (DFIG) system using a matrix converter controlled by direct duty ratio pulse-width modulation (DDPWM) scheme. DDPWM is a recently proposed carrier based modulation strategy for matrix converters which employs a triangular carrier and voltage references in a voltage source inverter. By using DDPWM, the matrix converter can directly and effectively generate rotor voltages following the voltage references within the closed control loop. The operation of the proposed DFIG system was verified through computer simulation and experimental works with a hardware simulator of a wind power turbine, which was built using a motor-generator set with vector drive. The simulation and experimental results confirm that a matrix converter with a DDPWM modulation scheme can be effectively applied for a DFIG wind power system.

• Journal of Applied Reliability
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• v.14 no.1
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• pp.37-43
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• 2014

This paper deals with a design of observer based fault detection filter for a boiler-turbine control system. The goal is to present a method for rapid sensor fault detection in order to enhance the reliability of boiler-turbine operation in the thermal power plant. Our fault detection filter can be designed via solutions of linear matrix inequalities. In order to demonstrate the efficacy of our design method, numerical simulations are provided.

• Journal of the Korean Institute of Telematics and Electronics
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• v.26 no.10
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• pp.1591-1597
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• 1989

Through the matematical alaysis of EX-NOR logic relation between the input vector and the memory matrix, we propose a new method for optical implementation of the bipolar Hopfield neural network model based on the optical vector-matrix multiplier.

• 한국정보디스플레이학회:학술대회논문집
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• 2009.10a
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• pp.83-86
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• 2009

BiNem$^{(R)}$ displays have entered volume manufacturing in 2009. Applications range from e-labels to e-readers. We have developed 6-inch $960{\times}720$ pixels passive matrix BiNem prototypes achieving 40 % brightness and fluid user interface based on partial image / dynamic pointer addressing. Active-matrix addressing is proposed to provide even faster operation.

• Information and Communications Magazine
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• v.7 no.3
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• pp.27-34
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• 1990

The $(L,\psi)$ feature description on the binary boundary air craft image is introduced of classifying 3-D object (aircraft) identification. Three types for associative matrix memories are employed and tested for their classification performance. The fast association involved in these memories can be implemented using a parallel optical matrix-vector operation. Two associative memories are based on pseudoinverse solutions and the third one is interoduced as a paralell version of a nearest-neighbor classifier. Detailed simulation results for each associative processor are provided.

• East Asian mathematical journal
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• v.37 no.3
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• pp.295-305
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• 2021

In this paper, we analyze the efficiency of a domain decomposition method for the two-dimensional telegraph equations. We formulate the theoretical spectral radius of the iteration matrix generated by the domain decomposition method, because the rate of convergence of an iterative algorithm depends on the spectral radius of the iteration matrix. The theoretical spectral radius is confirmed by the experimental one using MATLAB. Speedup and operation ratio of the domain decomposition method are also compared as the two measurements of the efficiency of the method. Numerical results support the high efficiency of the domain decomposition method.

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.4
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• pp.418-425
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• 2012

In this paper, efficient implementation of error correction code (ECC) processing circuits based on single error correction and double error detection (SEC-DED) code with check bit pre-computation is proposed for memories. During the write operation of memory, check bit pre-computation eliminates the overall bits computation required to detect a double error, thereby reducing the complexity of the ECC processing circuits. In order to implement the ECC processing circuits using the check bit pre-computation more efficiently, the proper SEC-DED codes are proposed. The H-matrix of the proposed SEC-DED code is the same as that of the odd-weight-column code during the write operation and is designed by replacing 0's with 1's at the last row of the H-matrix of the odd-weight-column code during the read operation. When compared with a conventional implementation utilizing the odd-weight- column code, the implementation based on the proposed SEC-DED code with check bit pre-computation achieves reductions in the number of gates, latency, and power consumption of the ECC processing circuits by up to 9.3%, 18.4%, and 14.1% for 64 data bits in a word.

• Journal of the Korean School Mathematics Society
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• v.7 no.2
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• pp.81-97
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• 2004

This paper is a study on the understanding process of「Matrix and Graph」on discrete mathematics using TI-92 calculator. For this purpose, we investigated the understanding process of two middle school students learning the concepts of matrix and graph using TI-92 calculator. In this process, we collected qualitative data using recorder and video camera. Then we categorized these data as follows: students' attitude related to using technology, understanding process of meaning, expression and operation of matrix and graph, mathematical communication, etc. From this, we have the following conclusions: First, students inquired out the meaning and role of matrix by themselves using calculator. We could see that calculator can do the role of good learning partner to them. Second, students realized their own mistakes when they used calculator on the process of learning matrix. So we found that calculator could form the self-leading learning circumstance on learning matrix. Third, calculators reinforce the mathematical communication in learning matrix and graph. That is, calculator could be a good mediator to reinforce mathematical communication between teacher and students, among students on learning matrix and graph.