• 경영과학
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• 제12권1호
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• pp.1-17
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• 1995

The success of cell manufacturing applications in FMS rests on the effective cell formation to maintain the independent relations both between machine cells and between part families. This paper presents an integrated method for concurrent formation of cells and families with no E.E (Exceptional Element) in FMS with alternative routings. To determine the maximum number of cell and family with no E.E, mathematical conditions and properties are derived. New concept of nonsimilarity is introduced for each machine and part based on machine-operation incidence matrix and part-operation incidence matrix. To concurrently form the cells and families, integer programming based mathematical models are developed. For the predetermined number of cell or family, model I is used to identify whether E.E exists or not. Model II forms cells and families considering only nonsimilarity. But model III can consider nonsimilarity and processing times. The proposed method is tested and proved by using numerical examples.

• Journal of Information Processing Systems
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• 제16권6호
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• pp.1359-1371
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• 2020

In transmitting and receiving such a large amount of data, reliable data communication is crucial for normal operation of a device and to prevent abnormal operations caused by errors. Therefore, in this paper, it is assumed that an error correction code (ECC) that can detect and correct errors by itself is used in an environment where massive data is sequentially received. Because an embedded system has limited resources, such as a low-performance processor or a small memory, it requires efficient operation of applications. In this paper, we propose using an accelerated ECC-decoding technique with a graphics processing unit (GPU) built into the embedded system when receiving a large amount of data. In the matrix-vector multiplication that forms the Hamming code used as a function of the ECC operation, the matrix is expressed in compressed sparse row (CSR) format, and a sparse matrix-vector product is used. The multiplication operation is performed in the kernel of the GPU, and we also accelerate the Hamming code computation so that the ECC operation can be performed in parallel. The proposed technique is implemented with CUDA on a GPU-embedded target board, NVIDIA Jetson TX2, and compared with execution time of the CPU.

• 한국데이타베이스학회:학술대회논문집
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• 한국데이타베이스학회 1999년도 춘계공동학술대회: 지식경영과 지식공학
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• pp.353-359
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• 1999

We present a matrix-based inference algorithm suitable for electronic commerce applications. For this purpose, an Extended AND-OR Graph (EAOG) was developed with the intention that fast inference process is enabled within the electronic commerce situations. The proposed EAOG inference mechanism has the following three characteristics. 1. Real-time inference: The EAOG inference mechanism is suitable for the real-time inference because its computational mechanism is based on matrix computation. 2. Matrix operation: All the subjective knowledge is delineated in a matrix form. so that inference process can proceed based on the matrix operation which is computationally efficient. 3. Bi-directional inference: Traditional inference method of expert systems is based on either forward chaining or backward chaining which is mutually exclusive in terms of logical process and computational efficiency. However, the proposed EAOG inference mechanism is generically bi-directional without loss of both speed and efficiency. We have proved the validity of our approach with several propositions and an illustrative EC example.

• 전자공학회논문지A
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• 제32A권10호
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• pp.73-80
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• 1995

In this paper, a synthesis tool using matrix operations for designing multi-level Reed Muller circuits is described which has been named as MRM (Multi-level Reed Muller Minimizer). The synthesis method which uses matrix operations has advantages in effectively minimizing chip area, delay optimization and fault detection capability. However, it uses only truth-table type maps for inputs, synthesizing only small circuits. To overcome the weakness, our method accepts two-level description of a logic function. Since the number of cubes in the two-level description is small, the input matrix becomes small and large circuits can be synthesized. To convert two-level representations into multi-level ones, different input patterns are extracted to make a map which can be fed to the matrix operation procedure. Experimental results show better performance than previous methods. The matrix operation method presented in this paper is new to the society of Reed Muller circuits synthesis and provides solid mathematical foundations.

• Nuclear Engineering and Technology
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• 제48권2호
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• pp.386-403
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• 2016

The safety of nuclear power plants is analyzed by a probabilistic risk assessment, and the fault tree analysis is the most widely used method for a risk assessment with the event tree analysis. One of the well-known disadvantages of the fault tree is that drawing a fault tree for a complex system is a very cumbersome task. Thus, several graphical modeling methods have been proposed for the convenient and intuitive modeling of complex systems. In this paper, the reliability graph with general gates (RGGG) method, one of the intuitive graphical modeling methods based on Bayesian networks, is improved for the reliability analyses of dynamic systems that have various operation modes with time. A reliability matrix is proposed and it is explained how to utilize the reliability matrix in the RGGG for various cases of operation mode changes. The proposed RGGG with a reliability matrix provides a convenient and intuitive modeling of various operation modes of complex systems, and can also be utilized with dynamic nodes that analyze the failure sequences of subcomponents. The combinatorial use of a reliability matrix with dynamic nodes is illustrated through an application to a shutdown cooling system in a nuclear power plant.

• 상하수도학회지
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• 제22권4호
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• pp.437-444
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• 2008

Many other countries have investigated the new backwash water treatment process to save the existing water resource. There are various methods for reusing backwash water, but the membrane system has received the most interest for its efficiency. The objective of this study was to certify the application of membrane filtration system for the backwash water treatment. The experiment equipment was composed of Lab scale tubular membrane filtration system. Generally, cross-flow operation mode is used in the tubular membrane system but cross-flow operation mode demands high electric cost mainly for the pump energy. So to cut off electric cost, dead-end operation mode was used in this experiment. Filtration and bleed operation cycle was used in this membrane system. Backwash water was concentrated during the filtration process and when backwash water reached our target suspended solid concentration, it was discharged from this system. For efficient operation of filtration and bleed, mathematical matrix was drawn up and with this matrix we could simulate various sets of filtration and bleed time.

• 대한임베디드공학회논문지
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• 제17권6호
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• pp.367-374
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• 2022

The acceleration of neural networks has become an important topic in the field of computer vision. An accelerator is absolutely necessary for accelerating the lightweight model. Most accelerator-supported operators focused on direct convolution operations. If the accelerator does not provide GEMM operation, it is mostly replaced by CPU operation. In this paper, we proposed an optimization technique for 2-stage tiling-based GEMM routines on VTA. We improved performance of the matrix multiplication routine by maximizing the reusability of the input matrix and optimizing the operation pipelining. In addition, we applied the proposed technique to the DarkNet framework to check the performance improvement of the matrix multiplication routine. The proposed GEMM method showed a performance improvement of more than 2.4 times compared to the non-optimized GEMM method. The inference performance of our DarkNet framework has also improved by at least 2.3 times.

• 전기학회논문지
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• 제56권3호
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• pp.524-530
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• 2007

This paper presents a new and simple method for sensorless operation of matrix converter drives using a constant air-gap flux and the imaginary power flowing to the motor. To improve low-speed sensorless performance, the non-linearities of a matrix converter drive such as commutation delays, turn-on and turn-off times of switching devices, and on-state switching device voltage drop are modelled using PQR transformation and compensated using a reference power control scheme. The proposed compensation method is applied for high performance induction motor drives using a 3 kW matrix converter system. Experimental results are shown to illustrate the feasibility of the proposed strategy.

• 한국지능정보시스템학회:학술대회논문집
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• 한국지능정보시스템학회 1999년도 춘계공동학술대회-지식경영과 지식공학
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• pp.353-359
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• 1999

We present a matrix-based inference alorithm suitable for electronic commerce applications. For this purpose, an Extended AND-OR Graph (EAOG) was developed with the intention that fast inference process is enabled within the electronic commerce situations. The proposed EAOG inference mechanism has the following three characteristics. 1. Real-time inference: The EAOG inference mechanism is suitable for the real-time inference because its computational mechanism is based on matric computation.2. Matrix operation: All the subjective knowledge is delineated in a matrix form, so that inference process can proceed based on the matrix operation which is computationally efficient.3. Bi-directional inference: Traditional inference method of expert systems is based on either forward chaining or backward chaining which is mutually exclusive in terms of logical process and exclusive in terms of logical process and computational efficiency. However, the proposed EAOG inference mechanism is generically bi-directional without loss of both speed and efficiency. We have proved the validity of our approach with several propositions and an illustrative EC example.

• 한국통신학회논문지
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• 제19권10호
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• pp.1861-1871
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• 1994

본 논문에서는 농담구조소(濃淡構造素)(GSE, grayscale structuring element)를 갖는 형태학 필터의 실시간 처리를 위한 알고리즘을 제안하였다. 제안된 알고리즘에서는 GSE로부터 유도된 basis matrix와 입력 샘플들로 구성된 input matrix를 이용하여 각 형태학 연산들을 소역행렬연산(local matrix operation)으로 새롭게 정의하고 있는데, 이를 이용하여 opening이나 closing과 같은 복합 형태학 연산들을 실시간으로 처리할 수 있음을 보였다. 제안된 알고리즘은 복원 형태학 연산들을 erosion과 dilation의 직렬조합(cascade combination)으로 처리하던 기존의 방법에 비해 적은 메모리를 필요로 하면서도, 출력을 얻기까지의 지연(遲延)(delay)이 훨씬 적다는 장점을 갖는다. 또한 본 논문에서는 형태학 필터를 VLSI로 구현하기 위한 효율적 방안을 제안하였다. 제안된 방법에서는 p-bit으로 표현되는 신호에 대한 형태학 연산을 p개의 이진(binary) 형태학 연산자들의 조합으로 구현하였는데, 각 이진 연산자들은 MSB(most significant bit)부터 순차적으로 (bit-serial approach) 해당 레벨의 bit들을 처리하여 출력을 부를 구조로 이루어져 있다. 본 논문에서는 형태학 필터의 VLSI 구현에 있어서 제안된 방법이 기존의 Threshold Decomposition 방법 등에 비해 보다 효율적이라는 것을 보였다.