• Membrane Journal
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• v.31 no.2
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• pp.145-152
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• 2021

While there are increasing demands on biomolecules separation, resin chromatography lacks in terms of throughput and membrane chromatography is an alternative with high binding capacity and enhanced mass transfer properties. Unlike typical membrane processing, where the performance can only be empirically assessed, understanding how mechanisms work in membrane chromatography is decisive to design biospecific processing. This short review covers three separation mechanisms, including affinity interaction modes for selectively capturing bulk molecules using biospecific sites, ion exchange modes for binding biomolecules using net charges and hydrophobic interaction modes for binding targeted, hydrophobic species. The parameters in designing membrane chromatography that should be considered operation-wise or material-wise, are also further detailed in this paper.

• Membrane Journal
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• v.25 no.6
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• pp.524-529
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• 2015

In this study transmembrane pressure (TMP) was measured with respect to operational time by applying the sinusoidal flux continuous operation (SFCO) for the hollow fiber membrane. The hollow fiber module which has $100cm^2$ of effective area and $0.45{\mu}m$ nominal pore size was submerged in the activated sludge solution of MLSS 5,000 mg/L. The critical permeate flux was measured as $26.6L/m^2{\cdot}hr$ by the method of continuous flux step change. TMPs of the filtration/relaxation (FR), FR with backwashing (FR/BW) and SFCO modes were measured. The SFCO mode was more effective than FR and FR/BW modes below the critical permeate flux such as 15, 20 and $25L/m^2{\cdot}hr$. However, the FR/BW was confirmed as more effectively fouling controlled mode than SFCO mode above the critical permeate flux.

• The Journal of Korean Institute of Electromagnetic Engineering and Science
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• v.30 no.2
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• pp.141-151
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• 2019

In this study, we propose a performance analysis of a quadrature-polarimetric(quad-pol) synthetic aperture radar(SAR) system for wide-swath operation mode and compare it with a single-pol system based on the operation mode. To achieve a shorter revisit time for an SAR satellite, we must observe a wide area, and two SAR operation modes exist for this purpose, which are called ScanSAR and SweepSAR. In general, a quad-pol SAR system can obtain a greater variety of information about a target than a single-pol system. Because this system affects system performance parameters, analyzing these effects is required. Based on a performance analysis of the wide-swath quad-pol SAR system, the system parameters and appropriate operation mode can be selected to satisfy the performance requirements.

• Journal of Space Technology and Applications
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• v.4 no.2
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• pp.169-183
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• 2024

Korea Astronomy and Space Science Institute (KASI) developed the Geochang satellite laser ranging (SLR) system for the scientific research on the space geodesy as well as for the national space missions including precise orbit determination and space surveillance. The operation system was developed based on the server-client communication structure, which controls the SLR subsystems, provides manual and automatic observation modes based on the observation algorithm, generates the range data between satellites and SLR stations, and carry out the post-processing to remove noises. In this study, we analyzed the requirements of operation system, and presented the development environments, the software structure and the observation algorithm, for the server-client communications. We also obtained laser ranging data for the ground target and the space geodetic satellite, and then analyzed the ranging precision between the Geochang SLR station and the International Laser Ranging Service (ILRS) network stations, in order to verify the operation system.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.17 no.5
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• pp.1203-1212
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• 2013

In this paper, an intra prediction hardware architecture is proposed to reduce computational complexity of intra prediction in HEVC decoder. The architecture uses shared operation units and common operation units and adopts a fast smoothing decision algorithm and a fast algorithm to generate coefficients of a filter. The shared operation unit shares adders processing common equations to remove the computational redundancy. The unit computes an average value in DC mode for reducing the number of execution cycles in DC mode. In order to reduce operation units, the common operation unit uses one operation unit generating predicted pixels and filtered pixels in all prediction modes. In order to reduce processing time and operators, the decision algorithm uses only bit-comparators and the fast algorithm uses LUT instead of multiplication operators. The proposed architecture using four shared operation units and eight common operation units which can reduce execution cycles of intra prediction. The architecture is synthesized using TSMC 0.13um CMOS technology. The gate count and the maximum operating frequency are 40.5k and 164MHz, respectively. As the result of measuring the performance of the proposed architecture using the extracted data from HM 7.1, the execution cycle of the architecture is about 93.7% less than the previous design.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.20 no.6
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• pp.1163-1170
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• 2016

A hardware implementation of ultra-lightweight block cipher algorithm PRESENT which was specified as a standard for lightweight cryptography ISO/IEC 29192-2 is described. The PRESENT crypto-processor supports two key lengths of 80 and 128 bits, as well as four modes of operation including ECB, CBC, OFB, and CTR. The PRESENT crypto-processor has on-the-fly key scheduler with master key register, and it can process consecutive blocks of plaintext/ciphertext without reloading master key. In order to achieve a lightweight implementation, the key scheduler was optimized to share circuits for key lengths of 80 bits and 128 bits. The round block was designed with a data-path of 64 bits, so that one round transformation for encryption/decryption is processed in a clock cycle. The PRESENT crypto-processor was verified using Virtex5 FPGA device. The crypto-processor that was synthesized using a $0.18{\mu}m$ CMOS cell library has 8,100 gate equivalents(GE), and the estimated throughput is about 908 Mbps with a maximum operating clock frequency of 454 MHz.

• Korean Chemical Engineering Research
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• v.46 no.2
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• pp.233-247
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• 2008

Process monitoring technology is able to detect the faults and the process changes which occur in a process unpredictably, which makes it possible to find the reasons of the faults and get rid of them, resulting in a stable process operation, high-quality product. Statistical process monitoring method based on data set has a main merit to be a tool which can easily supervise a process with the statistics and can be used in the analysis of process data if a high quality of data is given. Because a real process has the inherent characteristics of nonlinearity, non-Gaussianity, multiple operation modes, sensor faults and process changes, however, the conventional multivariate statistical process monitoring method results in inefficient results, the degradation of the supervision performances, or often unreliable monitoring results. Because the conventional methods are not easy to properly supervise the process due to their disadvantages, several advanced monitoring methods are developed recently. This review introduces the theories and application results of several remarkable monitoring methods, which are a nonlinear monitoring with kernel principle component analysis (KPCA), an adaptive model for process change, a mixture model for multiple operation modes and a sensor fault detection and reconstruction, in order to tackle the weak points of the conventional methods.

• Journal of the Korea Institute of Information and Communication Engineering
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• v.21 no.4
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• pp.795-803
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• 2017

This paper describes a dual-standard cryptographic processor that efficiently integrates two block ciphers ARIA and AES into a unified hardware. The ARIA-AES crypto-processor was designed to support 128-b and 256-b key sizes, as well as four modes of operation including ECB, CBC, OFB, and CTR. Based on the common characteristics of ARIA and AES algorithms, our design was optimized by sharing hardware resources in substitution layer and in diffusion layer. It has on-the-fly key scheduler to process consecutive blocks of plaintext/ciphertext without reloading key. The ARIA-AES crypto-processor that was implemented with a $0.18{\mu}m$ CMOS cell library occupies 54,658 gate equivalents (GEs), and it can operate up to 95 MHz clock frequency. The estimated throughputs at 80 MHz clock frequency are 787 Mbps, 602 Mbps for ARIA with key size of 128-b, 256-b, respectively. In AES mode, it has throughputs of 930 Mbps, 682 Mbps for key size of 128-b, 256-b, respectively. The dual-standard crypto-processor was verified by FPGA implementation using Virtex5 device.

• The Journal of Korean Institute of Communications and Information Sciences
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• v.28 no.11C
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• pp.1077-1087
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• 2003

In this paper, we proposed an architecture of a cryptosystem with various operating modes for the network security and implemented in hardware using the ASIC library. For configuring a cryptosystem, the standard block ciphers such as AES, SEED and 3DES were included. And the implemented cryptosystem can encrypt and decrypt the data in real time through the wired/wireless network with the minimum latency time (minimum 64 clocks, maximum 256 clocks). It can support CTR mode which is widely used recently as well as the conventional block cipher modes such as ECB, CBC and OFB, and operates in the multi-bit mode (64, 128, 192, and 256 bits). The implemented hardware has the expansion possibility for the other algorithms according to the network security protocol such as IPsec and the included ciphering blocks can be operated simultaneously. The self-ciphering mode and various ciphering mode can be supported by the hardware sharing and the programmable data-path. The global operation is programmed by the serial communication port and the operation is decided by the control signals decoded from the instruction by the host. The designed hardware using VHDL was synthesized with Hynix 0.25$\mu\textrm{m}$ CMOS technology and it used the about 100,000 gates. Also we could assure the stable operation in the timing simulation over 100㎒ using NC-verilog.

• The Transactions of the Korean Institute of Power Electronics
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• v.19 no.5
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• pp.399-406
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• 2014

This study investigates the structure and operation of the ITER VS converter and proposes a sequence control method for six series-connected VS converters to reduce reactive power. The operation and the proposed sequence control method are verified through RTDS simulation. The ITER VS converter must supply voltage/current to the superconducting magnets for plasma current vertical stabilization, and the four-quadrant operation must proceed without a zero-current discontinuous section. The operation mode of the VS converter is separated into a 12- and 6-pulse circulating current and transition modes according to the size of the load current. The output voltage of the unit VS converter is limited because of the rated voltage; however, the superconducting coil must increase the operating output voltage. Thus, the VS converter must be connected in a 6-series to provide the required operating output voltage. The output voltage of the VS converters is controlled continuously; however, reactive power is limited within a minimized value of the grid. In this study, the unit converter is compared with converters connected in a 6-series to determine a suitable sequence control method. The output voltage is the same in all cases, but the maximum reactive power is reduced from 100% to 73%. This sequence control method is verified through RTDS simulation.