• Title/Summary/Keyword: one-chip

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Study on Early Adhesive Characteristic of Chip Seals Using a Surface Energy Approach (표면 에너지 원리를 이용한 칩실 포장의 초기 점착력 특성 연구)

  • Im, Jeong Hyuk
    • International Journal of Highway Engineering
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    • v.17 no.6
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    • pp.47-54
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    • 2015
  • PURPOSES : The objective of this study is to evaluate the early adhesive characteristic of asphalt emulsions, including polymer-modified emulsions, for chip seals using the surface energy concept, the bitumen bond strength (BBS) test, and the Vialit test. METHODS : Two general methods, the BBS test and Vialit test, were applied to investigate the bond strength and the aggregate loss, respectively. A new theory, the surface free energy (SFE) theory, was used to evaluate the adhesive characteristic between the emulsion and the aggregate. Based on the theory, the contact angles were measured, and then the surface energy components were calculated. Using those components, the work of adhesion (Wa) was calculated for each emulsion. To ensure reliable results, all the tests were performed under the same conditions, i.e., at $25^{\circ}C$ for 240 minutes of curing time. For the materials, three emulsions (CRS-2, CRS-2L, and CRS-2P) and one aggregate type (granite) were employed. RESULTS AND CONCLUSIONS : Under the same conditions, the modified emulsions showed better adhesive characteristics and curing behaviors than the unmodified emulsions. In addition, there was no significant difference between the various modified emulsions. One of the important findings is that the analysis by Wa presents more sensitive results than other methods. The results of the Wa showed that the CRS-2P emulsion has the best adhesive characteristics. Consequently, the use of modified emulsions for chip seals could prevent aggregate loss and allow open traffic earlier.

Design of MAC Chip for AWG Based WDM-PON - I : Input/Output Nodule (AWG 기반 WDM-PON을 위한 MAC 칩 설계- I: 입출력 모듈)

  • Yang, Won-Hyuk;Han, Kyeong-Eun;Kim, Young-Chon
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.33 no.6B
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    • pp.456-468
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    • 2008
  • In this paper, we design Input/Output modules as a preference work for implementation of hybrid two stage AWG based WDM-PON and verify operations of each function modules through the logic simulation. This WDM-PON system provides service to 128 ONUs through 32 wavelength and one wavelength is shared for upstream transmission with four ONU while each wavelength is allocated to each ONU for downstream transmission. The designed WDM-PON MAC chip is based on sub-MAC which consists of one control unit and reception unit and four transmission unit. To design the reception and transmission unit of sub-MAC, we define the functions of the sub-MAC, pins of the modules, control signal and timing of each signal. We intend to design MAC chip with 1Gbps transmission rate. Thus the designed MAC chip is worked on 125MHz clock rate. We define FSM and design Input/Output modules with VHDL. The logic simulation of the modules is executed by the ModelSIM simulator.

Research on the Main Memory Access Count According to the On-Chip Memory Size of an Artificial Neural Network (인공 신경망 가속기 온칩 메모리 크기에 따른 주메모리 접근 횟수 추정에 대한 연구)

  • Cho, Seok-Jae;Park, Sungkyung;Park, Chester Sungchung
    • Journal of IKEEE
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    • v.25 no.1
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    • pp.180-192
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    • 2021
  • One widely used algorithm for image recognition and pattern detection is the convolution neural network (CNN). To efficiently handle convolution operations, which account for the majority of computations in the CNN, we use hardware accelerators to improve the performance of CNN applications. In using these hardware accelerators, the CNN fetches data from the off-chip DRAM, as the massive computational volume of data makes it difficult to derive performance improvements only from memory inside the hardware accelerator. In other words, data communication between off-chip DRAM and memory inside the accelerator has a significant impact on the performance of CNN applications. In this paper, a simulator for the CNN is developed to analyze the main memory or DRAM access with respect to the size of the on-chip memory or global buffer inside the CNN accelerator. For AlexNet, one of the CNN architectures, when simulated with increasing the size of the global buffer, we found that the global buffer of size larger than 100kB has 0.8x as low a DRAM access count as the global buffer of size smaller than 100kB.

Effects of Different Levels of Crushed Bamboo Chip on Performance and Carcass Characteristics in Holstein Steers (파쇄 대나무 급여수준이 젖소 거세우의 성장과 도체특성에 미치는 영향)

  • 안병홍;강춘성;추교문;조희웅
    • Journal of Animal Science and Technology
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    • v.48 no.3
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    • pp.401-414
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    • 2006
  • Twenty eight Holstein steers 12 months old and weighing about 300kg were andomly allotted into one of four groups being fed ammoniated rice straw(ARS) and substituted 30%, 40% and 50% crushed bamboo chip for ARS to determine the effects of different levels of bamboo chip on performance, digestibility and carcass characteristics. Daily weight gain was reduced as the substitution levels of bamboo chip for ARS as a roughage source increased but there were no differences in daily weight gain between steers fed ARS alone and 30% bamboo chip for ARS. Concentrates intakes were not different between treatments by the substitution levels of bamboo chip for the whole fattening period. Roughage intake tended to increase as the substitution levels of bamboo chip increased. Total feed intake was not affected by the substitution levels of bamboo chip. However, feed efficiency got worse with increasing levels of bamboo chip. Animals fed the roughage substituting 30% bamboo chip for ARS were higher in profit by 13% than animals fed ARS alone as a roughage source. Digestibilities of Dry matter(DDM) and crude fiber(DCF) were highest in animals fed ARS alone as a roughage source. DDM's were lower in higher substitution levels of crushed bamboo chip but there were no differences in DCF among animals fed different levels of bamboo chip as a roughage source. Crude protein digestibility was not affected by ammoniated rice straw or by the different levels of bamboo chip. Dressing percentage and backfat thickness were not affected by ammoniated rice straw or by the levels of bamboo chip but ribeye area was narrowed as the levels of bamboo chip increased. Beef color, fat color, texture, maturity and marbling score were not affected by feeding of ammoniated rice straw or by the levels of bamboo chip. According to these results, it may be concluded that profit can increase when Holstein bulls are castrated and roughage containing ammoniated rice straw plus 30% bamboo chip is offered.

Monitoring system of physical behavior for dementia patient

  • Tanaka, Motohiro;Murakami, Ryuya;Dong, Rue Shao;Ishimatsu, Takakazu
    • 제어로봇시스템학회:학술대회논문집
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    • 2003.10a
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    • pp.1968-1970
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    • 2003
  • In this paper we propose a system to forecast the dangerous behavior of the dementia patients. Basic idea of our approach is to measure the body movements of the dementia patients using the acceleration sensor. Based on the data measured, warning the care-givers about possible dangerous actions like falling down from the bed and slipping down onto the floor to some extent. The signals measured by the acceleration sensor are processed by a one-chip computer. Based on the diagnosis of the one-chip computer , alert signal is generated to the care-giver by a wire-less signal. The sensor is implemented in a compact body . Applicability of the system is now being examined at a nursing home.

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Design of the PID Controller Using Finite Alphabet Optimization (유한 알파벳 PID제어기 설계)

  • Yang, Yun-Hyuck;Kwon, Oh-Kyu
    • Proceedings of the KIEE Conference
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    • 2004.11c
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    • pp.647-649
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    • 2004
  • When a controller is implemented by a one-chip processor with fixed-point operations, the finite alphabet problem usually occurs since parameters and signals should be taken in a finite set of values. This paper formulates PID finite alphabet PID control problem which combines the PID controller with the finite alphabet problem. We will propose a PID parameter tuning method based on an optimization algorithm under the finite alphabet condition. The PID parameters can be represented by a fixed-point representation, and then the problem is formulated as an optimization with constraints that parameters are taken in the finite set. Some simulation are to be performed to exemplify the performance of the PID parameter tuning method proposed in this paper.

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Cooling Technique for Electronic Equipments using a small scale CPL heat pipe (소형 CPL 히트파이프를 이용한 전자장치 냉각 기술)

  • Kang, Sarng-Woo;Lee, Yoon-Pyo
    • Proceedings of the KSME Conference
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    • 2004.11a
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    • pp.1241-1246
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    • 2004
  • The heat flux on a chip is rapidly increasing with decreasing the size of one. It is necessary to properly cool the high heat flux chip. One of the promising cooling methods is to apply CPL heat pipes with porous materials, for example PVA, polyethylene, and powder sintered metal plate and with microchannels in the evaporator. A small scale CPL heat pipe with PVA as wick was designed and manufactured. Since the height difference between the evaporator and the condenser is a crucial parameter in the CPL heat pipes, the performance of the heat pipes depending on the parameter was investigated. The parameter is higher the performance is better. However, the improvement rate of the performance does not increase the increase rate of the height. In addition to, the parameter effect depending on heat input was investigated.

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Algorithms for Implementing One Chip Binary Image Processor (1칩 이진 영상 처리기 구현을 위한 알고리즘)

  • 조석팔;진용옥
    • The Journal of Korean Institute of Communications and Information Sciences
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    • v.17 no.3
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    • pp.297-306
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    • 1992
  • Algorithms for implementing one chip binary image processor has been studied. In this paper, image quality improvement algorithms, for the data pre-processed with shading and gamma correction after digitizing the analog signal from CCD or CIS, such as : Improved high quality binarization algorithm is suggested. Error diffusion algorithms for high quality half-tone images is analyzed, Fuzzy Theory based mixed mode algorithm is suggested.

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A Design of the drive speed control system using IGBT full-bridge dc-dc converter for the battery fork-lift truck. (IGBT full-bridge dc-dc 변환기를 이용한 전동지게차의 주행제어 시스템 개발)

  • Chun, Soon-Yung;Park, Sung-Ki
    • Proceedings of the KIEE Conference
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    • 1992.07b
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    • pp.1176-1178
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    • 1992
  • This paper shows enhanced working performance of the battery fork-lift truck by developing the IGBT full bridge dc-dc convertor using one-chip micro-processor. The PWM pulse is generated from a 16 bit one-chip micro-processor for the speed control of DC motor. In order to ensure the operation of IGBT and motor pecewisely, IGBT gate drive circuit was designed by using current limiting IC and hige voltage limit IC. And also It is able to regenerative braking.

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Design of Digital Filter One Chip I.C (DIGITAL FILTER ONE CHIP I.C.화 및 제작)

  • Park, Sang-Bong;Pack, In-Cheon;Park, Noo-Kyeong;Moon, Dait-Chul;Tchah, Kyun-Hyon
    • Proceedings of the KIEE Conference
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    • 1987.07b
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    • pp.1495-1498
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    • 1987
  • This paper described the design of register part, ROM and entire digital filter implementation by merging with ALU, control part last year. The register part consists of shift register, parallel load serial output register, multiplexer and selector, and we designed specially the 1024 memory cells ROM and decoder to decode the register data. Also, presented scaling algorithm to prevent the overflow.

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