• Journal of the Korean Society for Precision Engineering
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• v.11 no.1
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• pp.150-156
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• 1994

To meet the process requirement of semiconductor device manufacturing, it is necessary to improve the alignment accuracy in exposure equipments. We developed the excimer laser stepper and will describe the methodology for alignment measurement and experimental results. Our wafer alignment system consists of off-axis optics, TTL(Through The Lens) optics and high precision stage. Off-axis alignment utilizes the image processing and /or diffraction from thealign marks of off-centered chip area. On the other hand, TTL alignment can be used for the die-by-die alignment using dual beam interferometry. When only off-axis alignment was used, the experimental alignment error(lml+3 .sigma. ) was 0.26-0.29 .mu. m, and will be reduced down to 0.15 .mu. m by adding TTL alignment.

• Journal of Institute of Control, Robotics and Systems
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• v.6 no.1
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• pp.104-111
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• 2000

A fuzzy logic Run-by-Run(RbR) controller and an in -line wafer characteristics prediction scheme for the rapid thermal processing system have been developed for the study of process repeatability. The fuzzy logic RbR controller provides a framework for controlling a process which is subject to disturbances such as shifts and drifts as a normal part of its operation. The fuzzy logic RbR controller combines the advantages of both fuzzy logic and feedback control. It has two components : fuzzy logic diagnostic system and model modification system. At first, a neural network model is constructed with the I/O data collected during the designed experiments. The wafer state after each run is assessed by the fuzzy logic diagnostic system with featuring step. The model modification system updates the existing neural network process model in case of process shift or drift, and then select a new recipe based on the updated model using genetic algorithm. After this procedure, wafer characteristics are predicted from the in-line wafer characteristics prediction model with principal component analysis. The fuzzy logic RbR controller has been applied to the control of Titanium SALICIDE process. After completing all of the above, it follows that: 1) the fuzzy logic RbR controller can compensate the process draft, and 2) the in-line wafer characteristics prediction scheme can reduce the measurement cost and time.

• Tribology and Lubricants
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• v.32 no.2
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• pp.67-71
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• 2016

This study investigates the characteristics of the sapphire wafer chemical mechanical polishing (CMP) process. The material removal rate is one of the most important factors since it has a significant impact on the production efficiency of a sapphire wafer. Some of the factors affecting the material removal rate include the pressure, platen speed and slurry. Among the factors affecting the CMP process, we analyzed the trends in the material removal rate and surface roughness, which are mechanical factors corresponding to both the pressure and platen speed, were analyzed. We also analyzed the increase in the material removal rate, which is proportional to the pressure and platen speed, using the Preston equation. In the experiment, after polishing a 4-inch sapphire wafer with increasing pressure and platen speed, we confirmed the material removal rate via thickness measurements. Further, surface roughness measurements of the sapphire wafer were performed using atomic force microscopy (AFM) equipment. Using the measurement results, we analyzed the trends in the surface roughness with the increase in material removal rate. In addition, the experimental results, confirmed that the material removal rate increases in proportion to the pressure and platen speed. However, the results showed no association between the material removal rate and surface roughness. The surface roughness after the CMP process showed a largely consistent trend. This study demonstrates the possibility to improve the production efficiency of sapphire wafer while maintaining stable quality via mechanical factors associated with the CMP process.

• Journal of Electrical Engineering and Technology
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• v.10 no.1
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• pp.325-330
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• 2015

With approval from the Asia Pacific Metrology Program Working Group on Materials Metrology (APMP WGMM), an international comparison for sheet resistance standards for silicon wafers was firstly conducted among Korea Research Institute of Standards and Science (KRISS) in Korea, CMS/ITRI in Taiwan, and NIM in China, which are national metrology institutes (NMIs), from August 2011 to January 2012. The sheet resistance values of the standards are $10{\Omega}$, $100{\Omega}$, and $1000{\Omega}$; the measurement was conducted in sequence at KRISS, CMS/ITRI, NIM, and KRISS again using the four-point probe method with single and dual configuration techniques. The reference value for the measurement results of the three NMIs was obtained through averaging the values of the three results for each sheet resistance range. The differences between the reference value and the measured values is within 0.22% for $10{\Omega}$, 0.17% for $100{\Omega}$, and 0.12% for $1000{\Omega}$. Therefore, the international consistency for conducting sheet resistance measurements is confirmed within 0.22% through the APMP WGMM approved comparison.

• Journal of the Korean Institute of Telematics and Electronics A
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• v.29A no.11
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• pp.62-69
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• 1992

In this paper, a measurement system of surface flatness test using 2-Bucket algorithm phase-shifting interferometry is designed and constructed. In the conventional surface flatness test system using phase shifting interferometry, it is needed more than 3 fringe datas but we propose 2-Bucket algorithm phase-shifting interferometry which only uses two fringe datas. 2-Bucket algorithm uses the relative phase differences of the neighbour pixels. If we watch the result of phase-shift error test simulation, 2-Bucket algorithm has the same calculating values that 3-Bucket, 4-Bucket and 5-Bucket algorithm have them. Experiments have been carried out on the silicon wafer. The measurement of silicon wafer's surface flatness shows that the flatness topography using 2-Bucket algorithm is similar to that of other algorithms.

• Journal of the Semiconductor & Display Technology
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• v.14 no.1
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• pp.1-5
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• 2015

This paper deals with the residual stresses developed in an epoxy film deposited on Si wafer. First, chemically induced residual stresses due to the volumetric shrinkage in cross-linking resins during polymerization are treated. The curvature measurement method is employed to investigate the residual stresses. Then, thermally induced stresses are investigated along the interface between the epoxy film and Si wafer. The boundary element method is employed to investigate the whole stresses in the film. The singular stress is observed near the interface corner. Such residual stresses are large enough to initiate interface delamination to relieve the residual stresses.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.7 no.1
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• pp.47-52
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• 2008

We present a 3-D profiler specially devised for the profile measurement of rough surfaces that are difficult to be measured with conventional non-contact interferometer. The profiler comprises multiple two-point-diffraction sources made of single-mode optical fibers. Test measurement proves that the proposed profiler is well suited for the warpage inspection of microelectronics components with rough surface, such as unpolished backsides of silicon wafers and plastic molds of integrated-circuit chip package.

• Journal of the Korean Institute of Electrical and Electronic Material Engineers
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• v.18 no.9
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• pp.798-802
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• 2005

The plating shape in the opening of photoresist becomes gradated shape in the fountain plating system, because bubbles from the wafer surface are difficult to escape from the deep openings, vias. In this paper, the bubble flow from the wafer surface during plating process was studied and we designed the tilted electrode ring to get uniform bump height on all over the wafer and evaluated the film uniformity by SEM and $\alpha-step$. In a-step measurement, film uniformities in the fountain plating system and the tilted electrode ring contact system were $\pm16.6\%,\;\pm4\%$ respectively.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2014.05a
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• pp.759-762
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• 2014

반도체소자의 제조 공정 기술 중 구리패턴을 얻기 위해서 사용하는 화학.기계적 연마(CMP)를 이용한 평탄화와 연마 공정에서 Wafer에 도포된 구리의 두께를 실시간으로 측정하여 정밀하게 제어할 필요가 있는데, 이때 획득되는 센서값을 실제 두께 값으로 환산하는 계산과정에서 오차가 발생할 수 있다. 실제 측정 값에 근사한 값을 얻도록 단순평균을 이용한 방법, 이동 평균, 필터 들을 사용하여 결과를 비교하여 옹고스트롬 단위의 두께를 실시간으로 측정하는 제어 시스템의 편차를 줄이도록 하는 방법의 구현에 대해 기술한다.

• Journal of the Korea Academia-Industrial cooperation Society
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• v.17 no.6
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• pp.708-714
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• 2016

In today's semiconductor industry, manufacturing technology is being developed for the purpose of processing large amounts of data and improving the speed of data processing. The packaging process in semiconductor manufacturing is utilized for the purpose of protecting the chips from the external environment and supplying electric power between the terminals. Nowadays, the WLP (Wafer-Level Packaging) process is mainly used in semiconductor manufacturing because of its high productivity. All of the silicon dies on the wafer are subjected to a high pressure and temperature during the molding process, so that die shift and warpage inevitably occur. This phenomenon deteriorates the positioning accuracy in the subsequent re-distribution layer (RDL) process. In this study, in order to minimize the die shift, a vision inspection system is developed to collect the die shift measurement data.