• Proceedings of the Korean Society of Precision Engineering Conference
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• 2008.06a
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• pp.519-520
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• 2008

• Proceedings of the Korean Society of Precision Engineering Conference
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• 2011.06a
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• pp.749-750
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• 2011

• JSTS:Journal of Semiconductor Technology and Science
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• v.12 no.2
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• pp.168-174
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• 2012

This paper describes a novel global on-chip interconnect scheme, in which a one UI-delayed symbol as well as the current symbol is sent for easing the sensing operation at receiver end. With this approach, the voltage swing on the channel for reliable sensing can be reduced, resulting in performance improvement in terms of power consumption, peak current, and delay spread due to PVT variations, as compared to the conventional repeater insertion schemes. Evaluation for on-chip interconnects having various lengths in a 130 nm CMOS process indicated that the proposed on-chip interconnect scheme achieved a power reduction of up to 71.3%. The peak current during data transmission and the delay spread due to PVT variations were also reduced by as much as 52.1% and 65.3%, respectively.

• Journal of the Korean Society of Manufacturing Process Engineers
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• v.8 no.4
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• pp.14-19
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• 2009

Micro fluid channels are machined on quartz glass using powder blasting, and the machining characteristics of the channels are experimentally evaluated. The powder blasting process parameters such as injection pressure, abrasive particle size and density, stand-off distance, number of nozzle scanning, and shape/size of the required patterns affect machining results. In this study, the influence of the number of nozzle scanning, abrasive particle size, and blasting pressure on the formation of micro channels is investigated. Machined shapes and surface roughness are measured, and the results are discussed. Through the experiments and analysis, LOC are ettectinely machined on quartz glass using powder blasting.

• Journal of the Korean Wood Science and Technology
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• v.15 no.3
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• pp.44-55
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• 1987

In order to study the effect of sawdustboard combined with plastic chips, 0.5mm($T_1$), 1mm($T_2$), 1.4mm($T_3$) thick nylon fiber. polypropylene rope fiber(RP), and 0.23mm thick moth-proof polypropylene net fiber(NP) were cut into 0.5, 1, 2cm long plastic chips. Thereafter, sawdustboard combined with plastic chips prepared as the above and plastic non-combined sawdustboard(control) were manufactured into 3 types of one-, two-, and three layer with 5 or 10% combination level. By the discussions and results at this study, the significant conclusions of mechanical and physical properties were summarized as follows: 1. The MORs were shown in the order of 3 layer> 2 layer> 1 layer among plastic non-combined boards, and $T_3$ < $T_2$ < $T_1$ < RP (NP(5%) < NP(l0%) among plastic combined boards. In 2cm long plastic chip in 1 layer board, the highest strength through all the composition was recognized. 1 layer board showing the lower strength with 0.5cm plastic chip rendered to the bending strength improvement by 2 or 3 layer board composition. On the other hand, 2 or 3 layer combined with 1, 2cm long polypropylene net fiber chips incurred MOR's conspicuous decrease requiring optimum plastic chip combined level and consideration to combined type. 2. MOE in plastic non-combined 3 layer board exhibited sandwich construction effect by higher resin content application to surface layer in the order of 3layer>1layer>2layer with the highest stiffness of the board combined with polypropylene chip, while nylon chip-combined board had little difference from plastic non-combined board. In relevant to length and layer effect, 3 layer board combined with the 0.5cm long polypropylene net fiber chip in 5% and 10% combined level presented 34-43% and 44-76% stiffness increase against plastic non-combined board(control), respectively. Moreover, in 1 layer board, 30% stiffness increase with 10% against 5% combined level in the 1 and 2cm long polypropylene net fiber chip was obtained. 3. Stress at proportional limit(Spl) showing the fiber relationship (r: 0.81-0.97) between MOR presented in the order of 1 layer<2 layer<3 layer in plastic non-combined board. Correspondingly, combined effect by layer and plastic chip length was similar to MOR's. 4. Differently from previous properties(MOR, MOE, Spl). work to maximum load(Wml) of 2 layer board approached to that of 3 layer board. Conforming the above phenomenon. 2 layer combined with 0.5cm long polypropylene net fiber chip kept the greater work than 1 layer. The polypropylene combined board superior to nylon -and plastic non - combined board seemed to have greater anti - failing capacity. 5. Internal bond strength(IB), in contrast to MOR's tendency. showed in the order of T1

• Journal of the Korean Institute of Telematics and Electronics
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• v.27 no.8
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• pp.1201-1210
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• 1990

This paper proposes on-chip instruction and data cache memories on RISC reduced instruction set computer) architecture which supports fast instruction fetch and data read/write, and enables RISC processor under research to obtain high performance. In the execution of HLL(high level language) programs, heavily used local scalar variables are stored in large register file, but arrays, structures, and global scalar variables are difficult for compiler to allocate registers. These problems can be solved by on-chip Instruction/Data cache. And each cycle of instruction fetch, pad delay causes the lowering of the processors's performance. Cache memories are designed in CMOS technology and SRAM(static-RAM), that saves layout area and power dissipation, is used for instruction and data storage. To speed up and support RISC processor's piplined architecture efficiently, hardwired logic technology is used overall circuits i cache blocks. The schematic capture and timing simulation of proposed cache memorises are performed on Apollo DN4000 workstation using Mentor Graphics CAD tools.

• JSTS:Journal of Semiconductor Technology and Science
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• v.16 no.6
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• pp.832-841
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• 2016

The voltage-frequency island (VFI) design paradigm has strong potential for achieving high energy efficiency in communication centric manycore system-on-chip (SoC) design called network-on-chip (NoC). However, because of the diminished scaling of wire-dimension and supply voltage as well as threshold voltage in modern CMOS technology, the vulnerability to link failure in VFI NoC is becoming a crucial challenge. In this paper, we propose an energy-optimized topology generation technique for VFI NoC to cope with permanent link failures. Based on the energy consumption model, we exploit the on-chip communication traffic patterns and characteristics of link failures in the early design stage to accommodate diverse applications and architectures. Experimental results using a number of multimedia application benchmarks show the effectiveness of the proposed three-step custom topology generation method in terms of energy consumption and latency without any degradation in the fault coverage metric.

• Proceedings of the Korean Institute of Information and Commucation Sciences Conference
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• 2016.05a
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• pp.174-177
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• 2016

Wireless network-on-chip (WNoC) can alleviate critical path problem of existing typical NoCs by integrating radio-frequency module on router. In this paper, core-connection-aware genetic algorithm-based core and WIR mapping methodology at small world WNoC is presented. The methodology could optimize the critical path between cores with heavy communication. The 33% of average latency improvement is achieved compared to random mapping methodology.

• Transactions of the Korean Society of Mechanical Engineers A
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• v.28 no.6
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• pp.774-782
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• 2004

This article presents a numerical and experimental investigation for the single-phase forced laminar convective heat transfer through arrays of micro-channels in micro heat exchangers to be used for cooling power-intensive semiconductor packages, especially the stacked multi-chip modules. In the numerical analysis, a parametric study was carried out for the parameters affecting the efficiency of heat transfer in the flow of coolants through parallel rectangular micro-channels. In the experimental study, the cooling performance of the micro heat exchanger was tested on prototypes of stacked multi-chip modules with difference channel dimensions. The simulation results and the experiment data were acceptably accordant within a wide range of design variations, suggesting the numerical procedure as a useful method for designing the cooling mechanism in stacked multi-chip packages and similar electronic applications.

• Proceedings of the Korean Society of Machine Tool Engineers Conference
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• 2002.04a
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• pp.302-307
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• 2002

In end milling process, the undeformed chip section area and cutting forces vary periodically with phase change of the tool. However, the real undeformed chip section area deviates from the geometrically ideal one owing to cutter runout and tool shape error. In this study, a method of estimating the real undeformed chip section area which reflects cutter runout and tool shape error was presented during up-end milling of Inconel 718 using measured cutting forces. The specific cutting resistance, K. and $K_t$ are defined as the radial and tangential cutting forces divided by the modified chip section area. Both of $K_r$, and $K_t$ values become smaller as the helix angle increases from $30^\circ$ to $40^\circ$ Whereas they become larder as the helix angle increases from $40^\circ$ to $50^\circ$. On the other hand, the $K_r$, and $K_t$ values show a tendency to decrease with increase of the modified chip section area and this tendency becomes distinct with smaller helix angle.